Cloud native EDA tools & pre-optimized hardware platforms
Soni Kapoor, Technical Marketing Manager
SNUG World is almost here, and we have an incredible lineup! There are 200+ technical presentations, tutorials and panels across 18 technology tracks, all related to the latest and most significant trends in the industry: AI, automotive, cloud, custom-AMS, digital design, IP, low-power design, physical verification, security, signoff and silicon test and analytics, to name a few.
This blog will focus on custom and analog/mixed-signal (AMS)-centric presentations and convince you to attend SNUG World, which kicks off on April 20th.
As you know, analog design is getting tougher but the design schedules remain tight, and the technical challenges analog designers face continue to grow, especially when moving to advanced node technologies.
Synopsys Custom Design Platform team has been developing innovative technologies, to help unleash the productivity of custom design teams worldwide.
Several marquee customers have broken free from their legacy design environment in the last eighteen months and moved to Synopsys Custom Design Platform for custom and analog designs.
Some of those customers are presenting at SNUG World. Here is a brief introduction to the Custom-AMS track sessions.
Hany Elhak, senior director of Marketing at Synopsys, will kick off the program with an update on the latest circuit simulation for analog, mixed-signal and memory designs.
Next will be a panel discussion in which Aveek Sarkar, vice president of engineering at Synopsys and industry leaders will discuss the future of hardware for circuit simulation - is it more CPUs, bigger memory, the cloud or all the above? Join us and find out!
George Kokai, from NVIDIA, will share an update on the latest design challenges and their impact on simulation.
Kihoon Kim of Samsung Foundry, will highlight a new approach to improve simulation runtime for AMS designs dramatically .
Om Johari, from Intel, will showcase the collaboration workflow between Intel and Synopsys that helps AMS designers to run, analyze and debug circuit simulations in a very interactive and easy-to-use way reducing manual errors.
Kedar Janardan Dhori of STMicroelectronics will highlight the requirements for fault analysis and discuss how ST uses TestMAX CustomFault to ensure functional safety of embedded memory IPs for the automotive market.
Danish Shaikh of Western Digital will provide details how his team achieved more productivity using Custom Compiler, and easily resolved design migration and simulation challenges for their 7nm designs.
Day 1 will conclude with Randy Wolff of Micron Technology sharing a practical user-case on how they utilize comprehensive multi-domain analysis and cutting-edge StatEye with IBIS-AMI models to accomplish the challenging LPDDR5 signal integrity analysis.
Samad Parekh and Manu Pillai from the Synopsys custom design team will talk about how simulation results analysis is changing in the face of growing analog design complexity. Attend this session and learn about the latest capabilities of our design environment.
Denis Goinard, director of Applications Engineering at Synopsys, will present on how designers can avoid extra design iterations by catching potential electrical issues earlier during design. He will highlight the Synopsys Custom Design Platform’s unified workflow that brings signoff analysis into the design process.
Karun Sharma, director of Applications Engineering at Synopsys will demonstrate how to improve QoR and productivity for your analog layout with Custom Compiler’s productive and easy-to-use features for analog placement, routing and template-based design reuse. We call these technologies visually-assisted layout automation.
Jinman Kang of SK hynix will share how his team reduced design time by 3X after deploying a template-based analog layout flow.
Anjali S from Intel will present how they achieved significant productivity gain by deploying a new schematic-driven layout methodology.
Denis Keane of Xilinx will highlight how Xilinx accelerated their chip integration while improving SPEF quality for timing closure with Custom Compiler. His team is able to increase design reliability and reduce late-phase editing iterations, improving productivity and achieving design closure much faster with in-design analysis.
Seongkyun (Gabriel) Shin of Samsung Foundry will present Samsung’s advanced node AMS design reference flow. The flow demonstrates how Samsung Foundry customers can now take advantage of the most advanced circuit design features, reliability verification, automated layout, block and chip integration to improve design productivity.
Day 2 will conclude with Ofer Tamir of Tower Semiconductor presenting how Synopsys and Tower Semiconductor partner to enable mutual customer success. This collaboration enabled analog, RF and photonics design flows for the customers designing their next generation of products.
The last day of SNUG World will start with an exciting presentation from Jean-Christophe Lafont of STMicroelectronics. He will discuss how ST improved their memory verification flow using Synopsys AMS solutions.
Raed Sabbah of Micron Technology will give a talk on performing variability-aware reliability analysis. By using MOSRA with Monte Carlo, they can accurately predict device performance over time and improve the robustness of their designs. Raed will also join David Kao of Micron to discuss how modern FLASH memory designs face many challenges due to increasing complexity. They will highlight the collaboration between Micron and Synopsys teams to enable mixed-signal verification and comprehensive reliability analysis.
Chuan Lyu from Marvell Technology will demonstrate an easy-to-use co-simulation setup for analog-centric users, which provides improved productivity and ease-of-debugging.
Senthil Annamalai, senior staff Applications Engineer at Synopsys will present how StarRC with its advanced custom design and 3DIC capabilities for parasitic extraction, enables designers to achieve improved capacity, accuracy and productivity for complex designs.
Jack Quinn from Endura Technologies will bring the custom/AMS sessions to an exciting conclusion with a presentation about Custom Compiler’s User Defined Device (UDD) technology. He will discuss how the graphical UDD methodology allows Endura to develop highly reusable and programmable complex layout blocks on various technology nodes. They found that using UDDs was 2X more efficient than previous approaches, so it’s well worth joining this session to find out more!
That was a quick sneak peek into this amazing virtual event you are able to enjoy during April 20-22.
If you haven’t already, please register here https://www.snugworld2021.com and join your fellow engineers at SNUG World to hear the practical information you can use on your current projects and the inspiration to create next generation of awesome products.