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Testing advanced semiconductor devices is always challenging, but chips with large, embedded memories raise the bar even higher. AI applications, including those based on machine learning (ML), are particularly memory hungry. Thus, AI chips have large memories that require special care and attention during test planning to ensure that devices can be screened effectively on the manufacturing floor. This post describes how SiMa.ai™, an innovate developer of hardware and software AI solutions, used the Synopsys TestMAX SMS IP solution to address their memory test challenges.
Introduction to SiMa.ai
SiMa.ai focuses on scaling Physical AI across robotics, drones, automotive, industrial automation, aerospace and defense, smart vision, and healthcare. The company says, “We are shipping the industry’s best, purpose-built, software centric Physical AI HW/SW platform that is best in class in ease of use, performance, and power efficiency.” The company has produced two generations of system on chip (SoC) solutions. The first, MLSoc, was designed for vision ML applications at the edge.
The latest generation of silicon, MLSoC Modalix, supports multimodal AI and generative AI (GenAI) edge and cloud applications across a wide range of end markets. These chips are fabricated in 6nm technology and are highly complex. They contain multiple Arm processors, a Synopsys ARC processor for vision computation, 4 channels for MIPI devices, video encoding and decoding, a Machine Learning Accelerator (MLA) supporting both floating point and integer calculations, Ethernet and PCI Express (PCIe) connectivity, and 8MB of internal memory.
Project Challenges
SiMa.ai provides ML edge solutions for the rapidly evolving and highly competitive AI market, which sets high standards for their projects. The goal is always to achieve first-time-right silicon, with first-pass success for production parts. One key part of meeting this target is an effective chip test process, enabling rapid execution and reducing the risk of costly re-spins. Specifically, the team wanted to run built-in self-test (BIST) on their embedded memories quickly on first silicon, followed by efficient test of all the blocks in the design.
With a memory-heavy ML design and numerous IP blocks, SiMa.ai faced significant integration challenges. The team needed a test solution that easily integrates with heterogeneous blocks and ML hierarchies, helping manage complexity efficiently. They needed easy-to-use test tools that could support new algorithms, experiments, and bit mapping. The tools had to allow in-house team to adapt quickly and experiment as needed. The solution also had to enable a smooth transition to in-house testing, to control costs and reduce reliance on external design houses.
Fundamentally, SiMa.ai wanted to “shift left” the test process. A modular solution supporting implementation and verification at the RTL state would allow the team to perform complete memory, block-level, and full-chip testing early in the design cycle.
The Synopsys Solution
Synopsys SMS IP is a comprehensive, integrated test, repair, and diagnostics solution that supports repairable or non-repairable embedded memories across any foundry or process node. Silicon-proven in over a billion chips, SMS IP is a cost-effective solution for improving test quality and repairing manufacturing faults found in advanced processes. It enables a highly automated design implementation and diagnostic flow, including Synopsys Silicon Browser and Synopsys Yield Accelerator. SoC designers achieve quick design closure and significantly improve time-to-market and time-to-yield in volume production.
Synopsys SMS IP includes optimized test algorithms specifically targeted at increasing coverage for memory defects such as process variation and resistive faults that are prevalent at smaller process nodes. Key benefits to chip development teams include:
Faster validation: automated testbench and validation ensure rapid first-silicon bring-up
Advanced diagnostics: detailed failure analysis accelerates yield and volume ramp
Seamless integration: tight memory integration enables quick timing closure and efficiency
IoT ready: supports embedded flash BIST, enabling robust Internet of Things (IoT) applications
Error protection: ECC Compiler guards against transient errors for reliable operation.
Conclusion
Using the SMS IP solution, SiMa.ai was able to reach all their test-related project goals. They achieved rapid time to test by running memory BIST tests within two days of receiving silicon and testing all blocks in one week, demonstrating the speed and ease of the Synopsys solution. Optimized memory testing and rapid test bring-up streamlined processes, resulting in faster and more efficient testing, and accelerated the overall development cycle.
The SiMa.ai team found that the SMS IP proved flexible and simplified tool adoption. The solution’s intuitive interface and modular architecture enabled easy in-house testing and supported experimentation. SMS IP also managed complexity effectively. Seamless integration with ML and heterogeneous blocks allowed the team to efficiently handle their memory-heavy, IP-rich designs.
The Synopsys solution provided cost savings by enabling in-house test and reducing reliance on third-party services. It also provide SiMa.ai a competitive advantage: improved product performance has strengthened its position in the AI market.
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