Cloud native EDA tools & pre-optimized hardware platforms
The semiconductor industry is experiencing a massive shift in chip design from monolithic SoCs to multi-die systems that integrate heterogeneous dies in a single package. Multi-die systems provide a path for designers to efficiently deliver innovative products with unprecedented functionality. By reusing proven dies, designers can reduce risk, accelerate time to market, and rapidly create new product variants with optimized system power and performance. Synopsys is leading the industry transformation from monolithic system-on-chips (SoCs) to multi-die systems with a comprehensive and scalable solution for fast heterogeneous integration. The solution, including EDA tools and IP, enables early architecture exploration, rapid software development and system validation, efficient die/package co-design, robust and secure die-to-die connectivity, and improved manufacturing and reliability.
Optimized thermal, power, & performance with early exploration & partitioning
Rapid software development & validation with high-capacity emulation & prototyping
Efficient die/package co-design with unified exploration-to-signoff platform and robust IP
Improve heath, security & reliability with holistic test & lifecycle management solutions
Early and fast architecture exploration is at the heart of achieving multi-die system success. Design exploration and analysis for multi-die systems become more complex, going from one die to multiple dies in a package. Designers must efficiently explore the appropriate partitions and system-level interconnect fabric to realize best system performance for the target workloads. Reusing IP effectively to meet time-to-market and cost constraints, ensuring testability, and securing the multi-die system, are among some of the challenges that require fast and early analysis-driven exploration. Early architecture exploration and analysis for multi-die systems enables system designers to optimize partitioning for the best performance, minimize interconnect traffic, and perform efficient power and thermal planning.
Developing software for multiple dies in a system can be challenging. Having access to a proven virtual die model helps software teams quickly develop, integrate, and test the software. Assembling virtual models in a multi-die system prototype allows for efficient software bring-up, debug, and analysis. Software teams can run large amounts of software in lockstep with the hardware using a unified, hybrid emulation and prototype environment to reliably measure power, accelerate compile time, and ultimately validate their multi-die system.
The ability to seamlessly transition your designs from monolithic SoC to multiple dies in a package becomes paramount in maintaining target PPA and time-to-market. Using a highly integrated and scalable co-design and analysis platform can help you manage the implementation complexity of 10s of dies to potentially hundreds of millions of interconnections. It allows you to efficiently explore, implement and analyze your multi-die systems. Having access to standards-compliant IP with critical latency, PPA, interoperability and security features that meet a broad range of multi-die system requirements provides the fastest path to assembling known good dies in an advanced package.
The complexity of maintaining health and reliability increases in a multi-die system since one failed die can cause the whole system to fail. You must plan for system-level test and variability, and on-chip voltage and temperature monitoring. Testing, diagnosing, repairing, calibrating, and improving operational metrics at every phase of the multi-die system’s lifecycle will vastly help improve your system’s long-term health and reliability. In addition, access to traceability and analytics across multi-die systems for in-design, in-ramp, in-production and in-field optimization can help you improve cost, quality and reliability. Advancements in analytics will allow binning of high-quality and high-performing dies for consideration during package assembly of multi-die systems.
Proven technologies for architecture exploration, design, software development and system validation, verification, IP, test, and silicon lifecycle management.
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