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Radio waves are all around us, all the time, from wireless phones and Wi-Fi connections, to satellite navigation signals guiding us to travel the Earth and Bluetooth devices to radar sensing of remote objects and stormy weather. Each of these applications thrive on Radio Frequency (RF) Integrated Circuits (IC). Today’s RFICs are complex chips by themselves and hyperconvergence is combining RF, analog, and digital logic into single devices. All these trends are making the RF IC design and verification more challenging. Synopsys solutions help you design RF ICs with a complete front-to-back flow from concept to verified layout ready for manufacturing, including DesignWare IP for 5G SoCs.
With Synopsys Custom Design Family of products engineers are able to achieve a full design and verification flow for state-of-the-art RFICs. This video demonstrates the full flow with a 6 GHz Low Noise Amplifier (LNA) using GlobalFoundries 22FDX process technology. The demonstration includes LNA schematic, S parameter and Harmonic Balance (HB) simulations, layout and electromagnetic (EM) simulation, LVS checking, and layout parasitic extraction. Simulations on the layout extracted view are done to be sure LNA gain, noise and linearity specifications were met.
When receiving a faint signal from a satellite hundreds of kilometers above us, the RF Low Noise Amplifier (LNA) must have very low noise and high gain. When making a call in a moving vehicle, the RF circuits must perform in a dynamically changing environment to maintain safety and connection quality. To facilitate development of high-performance RF ICs, Synopsys Custom Design Family of products, including PrimeSim Continuum, provides support of advanced semiconductor technology node PDKs, including FinFET 16nm~3nm nodes as well as SOI (Silicon on Insulator) and SiGe (Silicon Germanium) technology nodes. PDKs and RF Reference Flows are provided by foundry partners for use in designing RF ICs.
To achieve superior RF performance, the RF transistor and inductor p-cells offered in a foundry PDK may need to be further customized to get the extra gain, power or Q-factor. Synopsys Custom Compiler supports user-defined devices to achieve the extra performance, and supports layout re-use with templates to for high productivity. The quality factor of inductive elements is key to achieve superior RF circuit performance. Custom Compiler integrates the industry leading VeloceRF tool from Ansys for the synthesis of high-Q inductors and low loss transmission lines on a given technology node, including single-ended and differential spiral inductors and transformers of square or octagonal shapes, with or without center taps. Transmission lines such as CPW, Microstrip, Stripline, shielded or non-shielded, can also be synthesized.
Many RF circuits are used in mission-critical applications where high safety and reliability must span the entire silicon lifecycle. The combination of high current and shrinking dimensions of RF transistors and inductors leads to higher current density with power dissipation. This creates issues of electromigration and heat generation leading to circuit reliability risk.To address potential reliability issues early on, PrimeSim Reliability analysis provides fast in-design and chip level electromigration/IR (EMIR) analysis, as well as production-proven and foundry-certified technologies such as high-sigma Monte Carlo, MOS aging to enable full lifecycle reliability verification.
IC Validator provides fast and high capacity physical verification and signoff checks. It runs DRC, LVS directly on OA database, performs full cross-probing and debugging, and advanced ESD (Electro-Static Discharge) checking with PERC (Programmable Electrical Rule Checking).
The RF frequencies used in wireless communications range from 400MHz to 7GHz, and extend to mm-wave bands of 24GHz~95GHz. While higher frequency bands provide wider bandwidth for faster data transmission, the circuits usually take longer design times due to more severe parasitic coupling effects. RF IC designers need faster design-to-signoff turn-around-time.
Synopsys PrimeSim simulation solution provides faster block and chip level simulations and faster closure with post-layout extracted view simulation.
Harmonic Balance (HB) analysis in PrimeSim SPICE is most efficient for simulating RF LNAs, PAs, Mixers, LOs, and for analyzing nonlinear mixer noise and oscillator phase noise. RF critical net extraction is done by full wave electromagnetic analysis tools such as Keysight RFPro and Ansys Exalto. Full wave electromagnetic extraction and StarRC extraction are stitched automatically into a single extracted view netlist for final signoff simulation with PrimeSim SPICE.
In Part I we introduce an RF design flow based on Synopsys Custom Design Family which is tightly integrated with Ansys EM solutions. This video describes specification of a LNA amplifier and demonstrates synthesis of the LNA inductor layout.
In Part 2 we will demonstrate EM modeling of inductors using Ansys RaptorX and then demonstrate Synopsys PrimeSim RFIC simulation results analysis using the PrimeWave Design Environment within Custom Compiler.
In Part 3 of this video series, we provide an overview of custom layout solutions, show post layout verification demonstrating DRC vs. LVS validation, sign-off of EM modeling, and demonstrate final RFIC simulation results within Custom Compiler.
This video discusses how CoreHW designed a fractional-N PLL IP with fundamental VCO frequency range of 19~20.25GHz with RF frequency range extended to 38~40.5GHz and 76~81GHz using the Synopsys Custom Design Family.