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Enabling a New Era of Innovation through Open Collaboration
Synopsys is a premier member of RISC-V International and is a supporter of the growth and development of RISC-V, an open-source instruction set architecture (ISA) that is changing the processor landscape. Synopsys provides comprehensive, ready-to-use design, verification, and IP solutions that enable designers to harness the full potential of the flexible ISA for efficient, high-performance RISC-V-based designs.
Key Benefits
Fast Architecture-Driven PPA Optimization
Accelerate Time-to-Market
Enabling Secure and Reliable Designs
Robust RISC-V Processor IP & Toolchain
Synopsys Solutions for RISC-V
Synopsys ARC-V Processor IP
Synopsys ARC-V™ processor IP includes high-performance, mid-range, and ultra-low power RISC-V processor options, as well as functional safety versions, to deliver optimal power-performance efficiency for a broad range of application workloads. Synopsys ARC-V Processor IP is supported by the growing RISC-V ecosystem, giving developers a menu of choices to build a flexible environment with all the required development tools. Also supported is the trusted Synopsys MetaWare Development Toolkit, which includes all of the components needed to develop, debug and optimize embedded software for ARC-V Processor-based designs.
Design and Implementation
Synopsys Fusion QuickStart Kits (QIKs) for Synopsys ARC-V and SiFive Intelligence™ X280 and Performance™ P550 processor IP include implementation scripts, reference guides, and a baseline floorplan so designers don’t need to start from scratch. Utilizing QIKs and leveraging the Synopsys Fusion Compiler™ RTL-to-GDSII design product and Synopsys Design Space Optimization (DSO.ai™) AI application for chip design can accelerate the development of RISC-V-based SoC designs.
Verification
Reference methodologies for the verification and debugging of RISC-V system designs are available now, along with Synopsys EDA flows, emulation and virtual prototyping solutions, and methodologies to further support RISC-V SoC verification. Collaborative efforts include: RISC-V verification methodology cookbook for Bluespec cores, "Understanding UVM Coverage for RISC-V Processor Designs" white paper, RISC-V and processor verification using ImperasDV verification solutions, and the industry-leading Synopsys VCS® simulation and Verdi® debug tools for improved efficiency (see news release).
Custom Processor Design
ASIP Designer helps teams build a custom RISC-V processor through architecture exploration. Key capabilities include rapid exploration of architectural choices, generation of an efficient C/C++ compiler-based software development kit that automatically adapts to every architectural change, and automatic generation of power and area-optimized, synthesizable RTL.
RTL Analysis, Exploration, and Optimization
RTL Architect is a multi-dimensional implementation prediction engine that enables RTL designers to predict the PPA and congestion impact of their RTL changes.
Interface & Verification IP
Thousands of customers trust Synopsys IP in their SoCs, minimizing risk and accelerating time to market. Synopsys provides the industry’s broadest portfolio of complete, silicon-proven IP solutions, with leading PPA and security for the most widely used interfaces such as PCI Express®, CXL, USB, Ethernet, DDR, HBM, Die-to-Die, CCIX, MIPI, HDMI, and Bluetooth.
Software Security
Synopsys Black Duck® software composition analysis solution helps design teams manage the security, quality, and license compliance risks that can come from using open-source and third-party code in applications and containers.