The DesignWare® Duet Packages of Embedded Memories and Logic Libraries include memory compilers, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs that enable designers to achieve the maximum performance with the lowest possible power consumption for their specific application. The High Performance Core (HPC) Design Kit contains a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three. In addition, the DesignWare STAR Memory System® provides an integrated built-in self-test (BIST) and repair solution that improves test quality and manufacturing yield, while the DesignWare STAR Hierarchical System automates hierarchical testing for analog/mixed-signal IP, digital logic blocks and interface IP on an SoC.
Synopsys also provides a comprehensive family of zero mask adder multi-time programmable (MTP), few-time programmable (FTP) and one-time programmable (OTP) non-volatile memory (NVM) IP in standard CMOS process technologies. DesignWare GPIO Libraries support multiple voltages and offer a full set of support cells (supply, corner spacers, diode breakers, and terminators).