Synopsys Foundation IP solution enables designers of consumer, mobile, and data centers & HPC applications that require high speed, low leakage, and low power to achieve the best combination of performance, power, and area (PPA) for their SoC designs.
Synopsys Foundation IP offering includes a broad offering of high-speed, high-density, ultra-high density memory compilers and specialty memories - eMRAMs, TCAMs, and multi-port memories. It also includes a complete standard cell library supporting multiple architectures, voltage thresholds (VTs), gate biases, and process voltage temperatures (PVTs).
The Synopsys Foundation IP High-Performance Core (HPC) Design Kit contains a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU, and DSP cores for maximum speed, smallest area, lowest power or optimum balance of all three.
Synopsys I/O Libraries support multiple voltages and offer a full set of support cells (supply, corner spacers, diode breakers, and terminators).
The Synopsys Duet Packages of Embedded Memories and Logic Libraries include standard cells, SRAMs, register files, ROMs, HPC Design Kits, Power Optimization Kits (POKs), and optional overdrive/low voltage PVTs, specialty memories, and memory built-in self-test (BIST) and repair that enable designers to achieve the maximum performance with the lowest possible power consumption for their specific application.
Synopsys also provides a comprehensive family of zero mask adder multi-time programmable (MTP), few-time programmable (FTP), and one-time programmable (OTP) non-volatile memory (NVM) IP in standard CMOS process technologies.