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Synopsys embedded ternary content addressable memory (TCAM) IP is a specialized memory technology that enables rapid and flexible data searches, helping networking designers meet the demand for wire-speed packet processing, access control lists, and other high-bandwidth delivery requirements. Synopsys TCAM compilers are available in geometries from 3nm to 180nm across multiple foundries.
High-Performance, High-Density Embedded CAM Compilers for Network Applications
Synopsys offers a broad range of feature-rich, high-performance, high-density embedded TCAM compilers. Our ternary CAM compilers provide high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.
User-Selectable Features
In addition to a full set of standard features, Synopsys TCAM compilers provide a comprehensive set of user-selectable features that are chosen at compile time. Designers can choose exactly the features that they need for a specific application to optimize performance, power or area (PPA).
- Partial pipelined search
- Priority encoder
- Redundancy
Synopsys CAM designs are available from 3nm to 180nm process geometries across multiple foundries, optimized to meet challenging PPA requirements of IDM and leading foundry processes. We can supply ternary CAM instances or compilers to fit the number of instances required.
Highlights & Key Features
- Duo architecture for extreme area and power reduction
- Multiple architectures available from 3nm to 180nm
- Flexible selection of width and depth with up to 1K entries and 160Kb macro size
- Easily cascadable to increase search depth without degradation in performance
- Single-cycle search, read and write operations
- Smart power management and partial-pipelined search option for reduced power
- Fast cycle and access time
- Valid-bit, global and local valid-bit reset
- Match-in and match-out flag for each entry
- Flexible masking (bit/group/global)
- Optimized layout for high density and high performance
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