Physical Verification

Using IC Validator

Comprehensive Physical Verification

In-Design Physical Verification at Leading Process Nodes

IC Validator offers a comprehensive DRC/LVS signoff solution that substantially reduces time-to-results while delivering excellent scalability, superior ease-of-use and broad runset support for all mainstream process nodes.

Industry Leading Performance

IC Validator is the proven high performance and comprehensive signoff physical verification solution. IC Validator’s high performance DRC and LVS engine delivers fastest physical signoff through excellent scalability to more than thousand CPU cores. Customers used IC Validator to achieve DRC signoff within hours on some of the industry’s largest designs with 20 billion+ transistors and die sizes greater than 800mm2.

Customer Experiences

IBM + -

IBM’s Experience with IC Validator DRC Explorer to Achieve Fastest DRC Results

Juniper + -

Juniper Highlights IC Validator’s Performance Benefit: Overnight Full Chip DRC and LVS

Nvidia + -

Nvidia’s Experience with IC Validator for Physical Signoff of Full-reticle GPU Designs

Socionext + -

Socionext Shares Their Experience with IC Validator for Excellent Performance Scalability

Synopsys Videos

Fusion Technology: Broadly Addressing the Challenges of 5-nm-and-Below Processes

Architected to extract maximum process entitlement for 5-nm-and-beyond processes’, Synopsys’ latest Fusion Technology is helping customers realize optimal full-flow, power, performance and area while accelerating their ever-important time-to-market.

How to Minimize the Impact of Metal Fill on Timing?

Metal fill insertion affects timing because of added capacitance. Balancing density requirements and timing on critical nets is crucial for timely design closure. IC Compiler II In-Design with signoff quality IC Validator metal fill minimizes the timing impact of metal fill and reduces overall design turnaround time.

How to Reduce the Amount of Time to Fix DRCs Near Tapeout?

In the later stages of design cycle, it is important to identify and fix DRC issues quickly to meet the tapeout schedule. This video discusses some techniques and best practices. Taking advantage of the integration of the IC Compiler II with signoff quality IC Validator DRC checking, designers can automatically fix DRC violations and improve turnaround time by automatically detecting changed ECO areas for incremental DRC checking.