Industry Leading Productivity


Synopsys IC Validator™ physical verification high-performance signoff solution improves productivity for customers at all process nodes, from mature to advanced. Synopsys IC Validator offers the industry’s best distributed processing scalability to over 4,000 CPU cores. The tool’s performance and scalability enabled some of the industry’s largest reticle limit chips with billions of transistors, same-day design rule checking (DRC), layout versus schematic (LVS), and fill turnaround time.

IC Validator is seamlessly integrated with the Synopsys Fusion Compiler™ RTL-to-GDSII solution and IC Compiler® II place and route system in the Synopsys Digital Design Family. This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment.

Key Benefits

Improved Accuracy
Detects and resolves design issues early in the design process, ensuring accuracy and precision without impacting performance or yield
Increased Productivity
Complete physical verification tasks in as little as half a day with half of the compute resources typically required
Seamless integration from synthesis to signoff, enabling faster design iterations and better collaboration among teams

What's new in IC Validator

Latest Videos

IC Validator PERC - Comprehensive Reliability Verification

Learn how IC Validator PERC enables designers to do a broad set of complex reliability verification checks at cell level, block level and full chip level.

EE Journal's Chalk Talk: Accelerating Physical Verification Productivity

In this episode of Chalk Talks Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process.

See How Rockley Photonics uses IC Validator

Watch this video to learn how Rockely used IC Validator for Silicon Photonics Verification.