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Industry Leading Productivity
IC Validator™ physical verification is a comprehensive and high-performance signoff solution that improves productivity for customers at all process nodes, from mature to advanced. IC Validator offers the industry’s best distributed processing scalability to over 4,000 CPU cores. The tool’s performance and scalability enabled some of the industry’s largest reticle limit chips with billions of transistors, same-day design rule checking (DRC), layout versus schematic (LVS), and fill turnaround time.
IC Validator is seamlessly integrated with the Synopsys Fusion Compiler™ RTL-to-GDSII solution and IC Compiler® II place and route system in the Fusion Design Platform™. This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment.
Resources
IC Validator PERC - Comprehensive Reliability Verification
Learn how IC Validator PERC enables designers to do a broad set of complex reliability verification checks at cell level, block level and full chip level.
EE Journal's Chalk Talk: Accelerating Physical Verification Productivity
In this episode of Chalk Talks Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process.
What's new in IC Validator
Demos
See how our customers are using IC Validator
Rockley Photonics
Silicon Photonics Verification with IC Validator
Toshiba
Faster DRC Closure With IC Validator
Barefoot Networks
IC Validator Physical Signoff on AWS Cloud