Physical Verification

Comprehensive Physical Verification

In-Design Physical Verification at Leading Process Nodes

Synopsys offers a comprehensive signoff DRC/LVS solution that substantially reduces time-to-results while delivering excellent scalability, superior ease-of-use and high programmability for easier runset development.

Comprehensive Physical Verification for Accelerating Innovation

Physical Verification with IC Validator in the Synopsys Galaxy™ Design Platform provides technology-leading, production-proven signoff solutions for design rule checking (DRC), connectivity verification layout-vs.-schematic (LVS), metal fill insertion, and design-for-manufacturability (DFM) enhancements. IC Validator is supported by all major foundries as a signoff solution for established-node designs, as well as advanced emerging-node designs at 20nm and below. It includes productivity links to leading design tools such as IC Compiler/IC Compiler II physical implementation, StarRC parasitic extraction, and Custom Compiler mixed-signal design. IC Validator’s In-Design physical verification speeds up design closure with timing-aware metal fill, DRC fixing, and double- and triple-patterning corrections within the IC Compiler and IC Compiler II environments.