Physical Verification

Using IC Validator

Comprehensive Physical Verification

Industry Leading Performance

IC Validator is a comprehensive and productivity boosting signoff physical verification solution improving productivity for customers at all process nodes from mature to advanced. IC Validator offers the industry’s best distributed processing scalability to over 2000 CPU cores. The tool’s performance and scalability has enabled some of the industry’s largest reticle limit chips with billions of transistors, same day design rule checking (DRC), layout versus schematic (LVS), and dummy fill turnaround time.

IC Validator physical verification is seamlessly integrated with Fusion Compiler™ RTL-to-GDSII solution and IC Compiler® II place and route system in the Fusion Design Platform. This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment. 

Featured Videos

Innovations in IC Validator for Advanced Node Physical Signoff

IC Validator DRC in the Cloud: Demo

Explorer DRC: Demo

Learn about latest technologies in IC Validator including; Explorer DRC, Live DRC, Scalability, Elastic computing to shorten time to tapeout by 2x.

Learn how to use Explorer DRC for super-fast design verification during SoC integration. Explorer enables designers to run DRC faster and isolate gross design weaknesses within hours instead of days.

Learn how to use IC Validator on the cloud to run DRC checking, scaling for faster performance, and Elastic CPU Management to add and remove CPUs on the fly.

How to Address Physical Signoff TAT Challenges for Today’s Advanced Node Designs

How to Do On-demand Signoff DRC for Custom Design Flows

How to Accelerate DRC Checking During SoC Integration

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