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Synopsys ZeBu‑200 is the industry’s fastest software-defined emulation platform, making it the ideal choice for executing complex and long‑running workloads needed for power and performance analysis as well as software/hardware validation. Delivering 2X performance improvement and 2X higher capacity per FPGA compared to the prior generation, the platform enhances emulation efficiency and boosts user productivity through faster time‑to‑model and advanced debug capabilities. It is a Synopsys EP‑Ready Hardware platform, enabling seamless upgrades to prototyping use cases through software‑defined features. Supporting the industry’s largest portfolio of interface solutions, the system includes transactor models, memory models, and speed adaptors for all major and emerging protocols. It covers all key HAV emulation use cases and is designed to validate complex, demanding workloads across AI, networking, automotive, consumer, and mobile applications.
What's New
Introducing Software-Defined Hardware-Assisted Verification: A New Benchmark for AI-Era Chip Design
Introducing Software-Defined Hardware-Assisted Verification
Hardware-Assisted Verification: Scaling for Modern Semiconductor Complexity
Accelerating AI Hardware: NVIDIA’s Journey with Synopsys HAPS Prototyping Solutions
Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles
Configurability for all Emulation and Prototyping Use Cases
ZeBu-200 is built on the Synopsys EP-Ready Hardware Platform that allows for software-defined upgrade to support HAPS-200 asynchronous clocking and HAPS ProtoCompiler, as well as the compliance and certification use case. Read more in our blog.
Users tend to do a lot of targeted functional verification as the RTL starts to come together. They need a platform that makes it easy and quick to port over their simulation environments and provide enough acceleration to cover the scenarios that are not ideal for simulation and formal environments. ZeBu’s simulation acceleration capabilities are utilized by industry’s major GPU, CPU, NPU, TPU providers along with other IP vendors in the networking, automotive sectors.
As RTL matures, users desire a platform that can provide orders of magnitude faster performance to cover long running suites. These regression suites serve the dual purpose of proving functional correctness, as well as getting closer to targets for coverage metrics. ZeBu’s transaction-based high-performance platform combines with its strong suite of industry’s latest Protocol Solutions (Transactor and Speed Adapters) to address these needs at some of the largest chip companies.
Starting from a reasonable level of RTL maturity, users start bringing up their software environments. There is a mix of bare-metal, low-level drivers and firmware, operating systems like Linux-Windows-Android, benchmark software application, general-purpose user applications that need to be brought up and proven functional. As the user persona evolves from being hardware-centric to a mix of hardware and software, ZeBu brings capabilities like Virtual Host Solutions to make the software developer feel at home. Combined with its superior performance, users can get very close to silicon like behavior.
As the designs near tape-out schedules, validation engineers get into a mode of mimicking their post-silicon lab environments. Their primary requirement is to enable hardware and software developers with a platform that could be used to serve as the highest-performance option in pre-silicon testing using real-world interfaces. They also want to build this platform as an option to reproduce and debug issues that they would encounter in the lab. Visibility into the design and being able to deterministically repeat those scenarios is key. ZeBu comes with a suite of strong debug technologies as well as a wide suite of speed adapters that have proven a capable partner for users to identify bugs and resolve them timely to not impact the customer’s time-to-market.
Users turn their attention to key design attributes of power and performance. They have long-running workloads that heavily exercise the DUT. By design, ZeBu can accurately model large number of clock domains prevalent in the modern SoC environments and yet provide the performance to execute these workloads.
Features & Benefits
- Performance: Up to 2X vs ZeBu EP
- Capacity: 2X higher capacity per FPGA vs. ZeBu EP
- Highest performance emulator with capacity scalable from 240 MG to 23 BG
- Advanced debug capabilities with improved trace memory, enabling at-speed capture of design waveforms and traces
- Support for all key emulation use cases: early RTL verification, RTL regressions, software bring-up, software/ hardware validation, power/performance analysis
- Configurable for prototyping use cases utilizing EP-Ready Hardware
What Our Customers Are Saying
"With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions. Synopsys HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are looking forward to scaling our HAPS-200 deployment to take full advantage for our software development teams.”
Narendra Konda
|Vice President, Hardware Engineering, NVIDIA
"The future of emulation and prototyping demands unprecedented performance, adaptability, and scalability. By integrating the AMD Versal Premium VP1902 adaptive SoC, with its industry-leading capacity*, performance, and debug capabilities, into Synopsys' EP-Ready platforms we're not only improving performance metrics, we're also transforming how engineering teams can validate and optimize their most ambitious new ASIC and SoC designs. Our longstanding partnership with Synopsys empowers design teams to tackle their most complex verification challenges, from AI/ML workloads to multi-die architectures, while dramatically accelerating time to market.”
Salil Raje
|Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
“Synopsys is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems.”
Kevork Kechichian
|Executive Vice President, Solutions Engineering, Arm
"Extending the modular HAV capabilities to the ZeBu Server 5 platform provides a scalable emulation roadmap to address the complexity challenges of validating AMD’s largest next-generation devices.”
Alex Starr
|Corporate Fellow, AMD
“SiFive has a very large and configurable portfolio of RISC-V CPU and AI core IP. We extensively test our IP using software workloads on HAPS, which means we can run trillions of cycles per day. As next generation CPUs and AI cores become larger and more complex, we need to efficiently map them onto larger and more powerful FPGAs. With its EP-Ready hardware HAPS-200 offers us an FPGA platform to do full system emulation for reference platforms that scale from small microcontrollers all the way to large scale data center designs.”
Albert Huntington
|Vice President, Platform Engineering, SiFive
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The EP-ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation."
Alex Starr
|Corporate Fellow, AMD
