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AI has fundamentally altered the business dynamics of chip design.
From hyperscale data centers to edge applications like autonomous vehicles and industrial robots, products and systems are now defined by the software and silicon at their core. Developing custom chips that hit aggressive, workload-specific KPIs — and getting them to market faster than competitors — has become the key to winning.
To do so, companies can’t wait for silicon to validate their chip designs. Not with the quadrillions of cycles required to optimize performance and power for specific AI workloads and full software stacks.
Hardware-assisted verification (HAV) has emerged as the keystone to pre-silicon validation.
By running emulation and FPGA-based prototyping prior to silicon availability, design teams can dramatically scale and accelerate validation cycles, reduce manufacturing risk, improve software bring-up, enhance power and performance, and speed time to market.
Synopsys HAV platforms are uniquely capable of enabling these outcomes, and they are continuously evolving to meet the escalating demands of AI.
Navigate AI Chip Development
Your essential guide to overcoming AI chip complexity and achieving successful silicon outcomes from design to deployment.
Three big steps forward
At Synopsys Converge 2026, we announced the next evolution of hardware-assisted verification: software-defined HAV.
This includes three upgrades to our HAV portfolio:
- Software-defined innovation — This new paradigm continually increases the performance, capability, and lifetime value of Synopsys ZeBu and HAPS systems without changing the underlying hardware. Verification speeds and debug productivity have been improved, capacity has been expanded for larger chip designs, new use case capabilities like Processor Subsystem Test Automation have been added, and more enhancements will be delivered over time — all through software updates.
- Expansion of our platform family — Two new 12 FPGA platforms (HAPS-200 12F and ZeBu-200 12F) supplant their 6 FPGA predecessors as the sweet spot for mainstream mobile, client, server, consumer, and edge AI chip designs as well as data center subsystems. Featuring EP-Ready hardware, the platforms can be configured to support all emulation and prototyping use cases.
- Capacity improvements for the AI era — With Modular HAV, the market-leading ZeBu Server 5 now scales to roughly 2X capacity to support mega chips (often 2.5D and 3D multi-die designs) purpose-built for data center, AI training and inference, GPU, custom accelerators, and network use cases.
Taken together, the announcements reflect an evolution in how verification infrastructure delivers value. Multiple layers are coalescing: hardware platform specialization with EP-Ready architecture; software stack flexibility with the capability to upgrade and improve key emulation and prototyping KPIs; and more use case capabilities.
These are transformative advances in how semiconductor players can use hardware-assisted verification to establish or protect their competitive position.
The pre-silicon imperative
It is hard to overstate the complexity of verification today. Mainstream designs scale well beyond 15 billion gates and mega designs for data canter compute and AI training now reach 50 billion gates or more, requiring long-running scenarios to validate performance and power under realistic conditions. Multi-die architectures and chiplets exponentially compound the number of building blocks, while interface standards — PCIe, HBM, LPDDR, Ethernet, and UCIe — evolve faster than hardware refresh cycles but demand at-speed validation.
At the same time, use cases for verification have broadened into new areas such as power/performance analysis, compliance/certification, software development for analog components, and fault emulation for safety aspects. All of them have distinct requirements for MHz, visibility, I/O realism, and analytics.
Most critically, semiconductor products are now defined by the specialized workloads they run — AI training versus inference, for instance, or vision versus text — with different sets of KPIs. Verification teams must prove a silicon design delivers the required performance, power, and functionality when running actual software — and do it pre-silicon, at scale, across billions of gates and trillions of cycles.
Engineering teams can’t risk vaporizing six to 12 months of work and millions of dollars by waiting until silicon is back from the fab only to discover an AI accelerator can’t efficiently run transformer models. Developers need to run full operating systems, drivers, middleware, and application workloads on verification platforms before manufacturing.
Synopsys HAV platforms deliver this capability, supporting emulation and FPGA-based prototyping for a “shift left” strategy in which software validation occurs during pre-silicon phases.
Software-defined innovation
As the demands of software-defined use cases and AI workloads grow, verification infrastructure must be able to change with it.
Software-defined HAV makes it possible. In the same way that software updates can now dramatically improve the performance of everything from cars to high-end GPUs already in use, our verification platforms can be further optimized without changing a single component.
Since 2023, software-defined innovations for our HAV products have delivered:
- Up to 2X performance improvements
- Up to 3X faster time-to-model
- 4X to 8X improvements in debug performance throughput via software-defined readback and coverage advances
Software-defined HAV also introduces new use case capabilities: alongside power and performance, platforms can now run HAV Test Solutions for cache coherency and subsystem verification. Through automation, teams reduce manual test writing and systematically stress complex subsystems to find more corner-case bugs that typically only emerge under long, highly concurrent workloads.
Our announcement at Converge establishes this model across our portfolio to increase performance on existing hardware, enhance software capabilities, and improve the lifetime value of ZeBu and HAPS systems.
Leveling up HAV
Software-defined HAV combines three important layers:
- Specialized hardware platforms with EP-Ready architecture
At the foundation are dedicated HAV platforms — ZeBu Server 5, ZeBu-200, and HAPS-200 — engineered for scale and modularity. They provide the raw resources to handle everything from IP blocks to multi-die mega designs, while EP-Ready hardware lets teams reconfigure the same base modules for either emulation or prototyping to right-size capacity and topology per use case and reuse assets as needs change. In addition, the platforms are tightly aligned with a rich portfolio of Synopsys Interface IP solutions for maximum flexibility and performance with real world connectivity.
- Flexible, upgradable software stacks
On top of hardware, software powers continuous improvement, increasing the lifetime value of the HAV platforms. Ongoing investments in compile, runtime, debug throughput, and hybridization unlock more capability and enable more use cases without swapping out hardware.
- Use case-centric capabilities
The top layer turns platforms and software into business outcomes through repeatable flows across verification scenarios. Modular and hybrid methodologies support everything from IP and subsystem validation to long-running AI workloads, compliance testing, and multi-die integration, allowing teams to reuse the same HAV infrastructure across projects and phases.
New engines for mainstream designs
As powerful as software improvements can be, they don’t eliminate the need for capacity scaling. Verification infrastructure must keep pace with growing chip complexity.
The two new systems we announced at Converge are made for the broad base of mainstream designs spanning mobile, client, server, consumer, and edge AI:
- HAPS-200 12F — A high-frequency prototyping platform with 12 AMD Versal Premium FPGAs, optimized for software bring-up, performance validation, and compliance testing.
- ZeBu-200 12F — An emulation platform with the same 12 FPGA EP-Ready architecture, delivering deep visibility for debug while supporting configurations up to approximately 23 billion gates.
The “12F” designation is a meaningful step up from the prior 6F generation, which are now best used for subsystems, mobile/client/server cores, microcontroller units (MCUs), and consumer designs. The new 12F systems are ideal for mainstream designs and edge AI that don’t require the massive multi-unit scaling needed for data center-class accelerators.
Scaling with Modular HAV
At the highest end of the market, hyperscalers need pre-silicon validation on very large setups for AI training accelerators, custom GPUs, and networking processors.
With growing demand for these mega designs, we also upgraded our flagship ZeBu Server 5. Through Modular HAV scaling and software, its market-leading design capacity has increased 2X to meet the challenges posed by complex multi-die architectures. Customers can mimic the modularity of multi-die designs, connect HAV engines at the edges of multi-die designs, verify the largest chip designs, and reliably run the longest pre-silicon AI workloads.
Re-engineering the strategic value of verification
Across our portfolio, our approach to hardware-assisted verification aims to deliver lasting strategic value on several fronts. First, software-defined HAV drives faster iteration cycles, with more compile-turns per day and shorter time-to-model. Teams move more quickly from RTL edits to running workloads, converging earlier on both functional correctness and software performance targets across the project lifecycle, translating into meaningful time-to-market advantages.
But software-defined HAV also delivers better asset efficiency. EP-Ready architecture lets organizations repurpose the same HAV racks for different phases of the flow — emulation-centric debug early on, then high-speed prototyping for software and interface validation as the design matures. Instead of maintaining separate platforms, customers keep utilization high.
Finally, software-defined HAV helps companies keep up with complexity. New protocols, analytics, and use case capabilities as well as performance, capacity, and debug improvements arrive as software updates on installed hardware platforms. Engineering leaders can continuously extend what their existing HAV footprint can do, even as designs, workloads, and standards keep changing.
In an era with rising semiconductor complexity and shrinking windows of opportunity, pre-silicon validation becomes a competitive advantage. As designs scale into tens of billions of gates and software workloads define product differentiation, the teams that can verify faster, reuse infrastructure more intelligently, and evolve capabilities without disruption are better positioned to win.
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