BLOG Dec 04, 2025/4 min read BLOG 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months By Shekhar Kapoor Tags: Multi-Die, RTL Synthesis, AI & Machine Learning, Test, About Synopsys, Physical Implementation, Interface IP, Foundation IP, Signoff, Customer Spotlight, Cloud, Silicon Lifecycle Management, Signal & Power Integrity, Design, Fusion Design Platform, 5nm and Below, HPC, Data Center, Silicon IP, Verification, 3DIC Design
BLOG Nov 06, 2025/5 min read BLOG 10 Tips for First-Pass Silicon Success in AI Chip Development By Rita Horner, Todd Koelling, Frank Schirrmeister Tags: Multi-Die, AI & Machine Learning, Test, Emulation, About Synopsys, Physical Implementation, Signoff, Virtual Prototyping, Engineering Central, Silicon Lifecycle Management, Design, HPC, Data Center, Silicon IP, Verification
BLOG Oct 15, 2025/4 min read BLOG Realize Up to 5x Faster Timing Signoff with FlexEDA By Manoz Palaparthi, Anuj Pant Tags: Cloud, Engineering Central, Design, Signoff
BLOG Sep 24, 2025/5 min read BLOG Hybrid Cloud for Chip Design: Agility, Cost Efficiency, and Data Continuity By Xingang Zhao, Varun Shah Tags: Cloud, AI & Machine Learning, Insights, Simulation, Design, About Synopsys, Signoff, Verification
BLOG Sep 11, 2025/3 min read BLOG What Is Local Layout Effect (LLE) and How Does It Impact Chip Design? By Chun-Soo Kim, Hoseong Kim Tags: Design, About Synopsys, Physical Implementation, 5nm and Below, Energy-Efficient SoCs, Signoff, Verification
BLOG Aug 14, 2025/5 min read BLOG How AI is Revolutionizing Analog and Digital Node Migrations By Sumit Vishwakarma Tags: AI & Machine Learning, Custom Implementation, Physical Verification, Design, About Synopsys, Manufacturing, AMS Simulation, Physical Implementation, Design Technology Co-Optimization, Signoff, Verification, Analog Design
BLOG Jul 01, 2025/5 min read BLOG RTL Signoff vs. Functional Signoff: What’s the Difference? By Bradley Geden, Manoz Palaparthi Tags: Multi-Die, RTL Synthesis, Static & Formal Verification, AI & Machine Learning, Debug, Physical Verification, Test, Simulation, About Synopsys, Energy-Efficient SoCs, Signoff, Design, Verification, Formal Verification
BLOG Jul 09, 2024/4 min read BLOG How to Use Python to Customize PrimeTime By Manoz Palaparthi Tags: Design, About Synopsys, Signoff
BLOG Apr 18, 2024/2 min read BLOG Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud By Anuj Pant Tags: Customer Spotlight, Cloud, Design, About Synopsys, Physical Implementation, Signoff
BLOG Mar 05, 2024/3 min read BLOG CalligoTech Enables Next-Gen Computing at Scale with Synopsys Digital Design Flow By Karan Shah, Irfan Shaikh Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Physical Verification, Test, Design, About Synopsys, Physical Implementation, Signoff, HPC, Data Center
BLOG Jun 13, 2023/4 min read BLOG Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads By Andy Tai, Ramesh Narayanaswamy Tags: Multi-Die, Design, About Synopsys, Physical Implementation, Signoff, HPC, Data Center, Verification
BLOG May 04, 2023/3 min read BLOG Synopsys Acquires Silicon Frontline Technology By Synopsys Editorial Staff Tags: Design, About Synopsys, Energy-Efficient SoCs, Signoff
BLOG Nov 02, 2022/4 min read BLOG Library Characterization for Advanced Process Chip Designs By Moninder Bansal Tags: Design, About Synopsys, Signoff
BLOG Oct 27, 2022/7 min read BLOG Why Sacrifice QoRs? Optimizing Design Signoff and Achieving Accurate Functional ECOs the Smarter Way By Makarand Patil, Avinash Palepu Tags: Design, About Synopsys, Signoff
BLOG Sep 27, 2022/4 min read BLOG Unifying Timing Constraints with FishTail Design Automation By Synopsys Editorial Staff Tags: Design, About Synopsys, Signoff, Verification
BLOG Sep 14, 2022/4 min read BLOG Enabling Edge Machine Learning Applications with SiMA.ai By Stelios Diamantidis Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Design, Emulation, About Synopsys, Signoff, Silicon IP, Verification
BLOG Aug 09, 2022/6 min read BLOG Accelerate SoC Design Flow with Functional ECO By Makarand Patil, Avinash Palepu Tags: Design, About Synopsys, Signoff
BLOG Feb 08, 2022/4 min read BLOG Powering Circuit Simulation Software with NVIDIA GPUs By Samad Parekh Tags: Customer Spotlight, Design, About Synopsys, Signoff
BLOG Sep 08, 2021/4 min read BLOG EDA Tools Help Students Build IC Design Skills By Synopsys Editorial Staff Tags: Custom Implementation, Physical Verification, Design, About Synopsys, Signoff
BLOG Aug 19, 2021/2 min read BLOG Improving Design Robustness with PrimeShield: A Discussion with Li Ding By Synopsys Editorial Staff Tags: Design, About Synopsys, Signoff
BLOG Jul 06, 2021/5 min read BLOG How Emulation Helps Find Power Bugs During SoC Verification By Alex Wakefield Tags: Static Verification, Simulation, Design, Emulation, About Synopsys, Energy-Efficient SoCs, Signoff, Verification, Virtual Prototyping, Formal Verification
BLOG Jun 28, 2021/3 min read BLOG Resistance Extraction with StarRC By Senthil Annamalai Tags: Design, Signoff
BLOG Apr 29, 2021/4 min read BLOG PrimeLib™ Next-Generation Library Characterization: A Discussion with Moninder Bansal By Synopsys Editorial Staff Tags: Design, About Synopsys, Signoff
BLOG Apr 20, 2021/3 min read BLOG Library Characterization Tool for Advanced Node SoC Design By Umang Doshi Tags: Multi-Die, Design, About Synopsys, Signoff
BLOG Mar 16, 2021/4 min read BLOG Emulation Technology for Faster SoC Power Verification By Johannes Stahl Tags: AI & Machine Learning, Design, Emulation, About Synopsys, 5G Wireless, Energy-Efficient SoCs, Signoff, Verification
BLOG Feb 18, 2021/2 min read BLOG StarRC Standalone Netlist Reducer: Achieving Practical Simulation Times By Senthil Annamalai Tags: Design, Signoff
BLOG Aug 25, 2020/2 min read BLOG StarRC Density Corner Value Proposition By Nitin Kalra Tags: Design, Signoff