Power semiconductor devices are at the heart of modern electronics, powering everything from smartphones to automobiles. These tiny high-voltage and high-current components are designed with meticulous care and attention to detail, and any errors in their design can lead to costly mistakes during fabrication. Growing demands from the portable and smart electronics market to constantly evolving high-performance computing systems place significant pressure on the power semiconductors to be utterly reliable and longer lasting.
The longer you expect an electronic device to work, the more investment goes into figuring out the best device material, device size, and the type of circuit you need to create. A good solution/platform is necessary to perform all the necessary steps in the process.
Along with power devices, another crucial step in the IC design process is electrical layout verification, which involves checking the integrity of the circuit against unconventional scenarios. These reliability checks are performed to understand if a circuit can withstand electrostatic discharge events without sustaining any damage or performance degradation. As chip designs grow larger and more complex, the number of unknowns increases, and designers must solve for more scenarios. Teams typically solve problems sequentially, which requires a lot of time and iterations. Today, both power device design and ESD verification are very ad-hoc processes, and designers are stitching together a variety of solutions to achieve their desired goal.
Our acquisition of Silicon Frontline Technology will enable us to immediately address critical performance and reliability challenges in the IC design process and offer end-to-end solutions for all electrical layout verification needs. In addition, Synopsys has gained core technologies to accelerate development of comprehensive system analysis solutions.
To learn more about what Silicon Frontline Technology will bring to Synopsys customers, we chatted with Hitesh Patel, senior director of product management for signoff solutions in the Synopsys EDA Group.