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Design Technology Co-Optimization

Our Design Technology Co-Optimization (DTCO) experts share insights on how the methodology helps semiconductor fabs lower costs while accelerating time to market for advanced process development.

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Plamen Asenov

Shela Aboud

Arun Venkatachar

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How AI is Revolutionizing Analog and Digital Node Migrations

BLOG Aug 14, 2025/5 min read

BLOG

How AI is Revolutionizing Analog and Digital Node Migrations

By Sumit Vishwakarma

Tags: AI & Machine Learning, Custom Implementation, Physical Verification, Chip Design Insights, Design, Manufacturing, AMS Simulation, Physical Implementation, Design Technology Co-Optimization, Signoff, Verification, Analog Design

The Integrated Design Challenge: Developing Chip, Software, and System in Unison

BLOG Jun 25, 2025/6 min read

BLOG

The Integrated Design Challenge: Developing Chip, Software, and System in Unison

By Synopsys Editorial Staff

Tags: AI & Machine Learning, Chip Design Insights, Design, Design Technology Co-Optimization, Silicon IP

Beyond Silicon: A Look at Alternative Semiconductor Materials

BLOG Feb 20, 2024/4 min read

BLOG

Beyond Silicon: A Look at Alternative Semiconductor Materials

By Shela Aboud

Tags: Chip Design Insights, Design Technology Co-Optimization

Minimize Design Risk and Achieve First-Pass Silicon Success on TSMC’s N3E Process

BLOG Jul 19, 2023/6 min read

BLOG

Minimize Design Risk and Achieve First-Pass Silicon Success on TSMC’s N3E Process

By Josefina Hobbs, Hezi Saar

Tags: Product Spotlight, Chip Design Insights, Design Technology Co-Optimization, Silicon IP

Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems

BLOG Jun 21, 2023/5 min read

BLOG

Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems

By Dermott Lynch

Tags: Multi-Die, Chip Design Insights, Design, Design Technology Co-Optimization

Why DTCO is Critical to Modern Memory Design Techniques

BLOG Aug 24, 2022/5 min read

BLOG

Why DTCO is Critical to Modern Memory Design Techniques

By Anand Thiruvengadam, Ricardo Borges

Tags: Custom Implementation, Chip Design Insights, Design, Design Technology Co-Optimization

What is Cryo-CMOS IP (Cryogenic semiconductor IP)?

BLOG Dec 14, 2021/4 min read

BLOG

What is Cryo-CMOS IP (Cryogenic semiconductor IP)?

By Plamen Asenov

Tags: Chip Design Insights, Quantum Computing, Design Technology Co-Optimization, Silicon IP

How DTCO Advances the Chip Design Process

BLOG Dec 12, 2021/3 min read

BLOG

How DTCO Advances the Chip Design Process

By Eric Chin

Tags: Chip Design Insights, Manufacturing, Design Technology Co-Optimization

2021 ERI Summit & Microsystems Technology Office Symposium

BLOG Oct 11, 2021/3 min read

BLOG

2021 ERI Summit & Microsystems Technology Office Symposium

By Ian Land

Tags: Aerospace & Government, Silicon Lifecycle Management, Chip Design Insights, Design, Design Technology Co-Optimization, Silicon IP, 3DIC Design

Defining the AI Era with the IBM Research AI Hardware Center

BLOG Oct 20, 2020/4 min read

BLOG

Defining the AI Era with the IBM Research AI Hardware Center

By Arun Venkatachar

Tags: Multi-Die, AI & Machine Learning, Emulation, Interface IP, Virtual Prototyping, Chip Design Insights, Design, Manufacturing, Design Technology Co-Optimization, Processor Solutions, Silicon IP, Verification, 3DIC Design

Browse by Tags

How AI is Revolutionizing Analog and Digital Node Migrations

The Integrated Design Challenge: Developing Chip, Software, and System in Unison

Beyond Silicon: A Look at Alternative Semiconductor Materials

Minimize Design Risk and Achieve First-Pass Silicon Success on TSMC’s N3E Process

Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems

Why DTCO is Critical to Modern Memory Design Techniques

What is Cryo-CMOS IP (Cryogenic semiconductor IP)?

How DTCO Advances the Chip Design Process

2021 ERI Summit & Microsystems Technology Office Symposium

Defining the AI Era with the IBM Research AI Hardware Center

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