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<title>Architecting AI Factories: Rack-Scale Design Series</title>
<link>https://www.synopsys.com/blogs/chip-design/architecting-ai-factories-series.html</link>
<dc:creator><![CDATA[Neeraj Paliwal, Charlie Matar]]></dc:creator>
<pubDate>Tue, 6 Oct 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["HPC, Data Center"]]></category>
<category><![CDATA["Silicon IP"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/architecting-ai-factories-series.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/architecting-ai-factories-spotlight-image-thumb?ts=1790791491732&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Explore how rack-scale design, power, cooling, interconnects, and data movement are reshaping AI factories and the economics of usable AI.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/architecting-ai-factories-series.html"> Architecting AI Factories: Rack-Scale Design Series</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Architecting AI Factories: The Rack Becomes the New Unit of Compute (Part 1 of 4)</title>
<link>https://www.synopsys.com/blogs/chip-design/ai-factory-rack-unit-of-compute.html</link>
<dc:creator><![CDATA[Neeraj Paliwal]]></dc:creator>
<pubDate>Tue, 6 Oct 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["HPC, Data Center"]]></category>
<category><![CDATA["Silicon IP"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/ai-factory-rack-unit-of-compute.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/architecting-ai-factories-blog-thumb-2?ts=1791301672067&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Learn why the rack is replacing the server as the unit of compute in AI factories, and how that shifts design toward cost per token and usable AI.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/ai-factory-rack-unit-of-compute.html"> Architecting AI Factories: The Rack Becomes the New Unit of Compute (Part 1 of 4)</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Introducing Synopsys Long-Horizon AgentEngineer&#8482; Solutions and Autopilot&#8482; Platform: Autonomous Engineering from Silicon to Systems</title>
<link>https://www.synopsys.com/blogs/chip-design/long-horizon-agentengineer-solutions.html</link>
<dc:creator><![CDATA[Anand Thiruvengadam]]></dc:creator>
<pubDate>Mon, 28 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["Engineering Central"]]></category>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Verification"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/long-horizon-agentengineer-solutions.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/synopsys-agentic-ai-portfolio-infographic-400x225?ts=1790599322961&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Discover how Synopsys long-horizon AgentEngineer solutions autonomously execute complex chip and systems engineering workflows.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/long-horizon-agentengineer-solutions.html"> Introducing Synopsys Long-Horizon AgentEngineer&#8482; Solutions and Autopilot&#8482; Platform: Autonomous Engineering from Silicon to Systems</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Agentic AI in Chip Design: From Execution to Orchestration (Part 4 of 4)</title>
<link>https://www.synopsys.com/blogs/chip-design/agentic-ai-engineering-orchestration.html</link>
<dc:creator><![CDATA[Thomas Andersen]]></dc:creator>
<pubDate>Thu, 24 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/agentic-ai-engineering-orchestration.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/agentic-ai-chip-design-blog-thumb-1?ts=1790930671951&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>See how agentic AI shifts engineers from execution to orchestration, judgment, and higher-value decision-making.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/agentic-ai-engineering-orchestration.html"> Agentic AI in Chip Design: From Execution to Orchestration (Part 4 of 4)</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Agentic AI in Chip Design: Why Knowledge Becomes the Advantage (Part 3 of 4)</title>
<link>https://www.synopsys.com/blogs/chip-design/agentic-ai-design-knowledge.html</link>
<dc:creator><![CDATA[Thomas Andersen]]></dc:creator>
<pubDate>Tue, 22 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/agentic-ai-design-knowledge.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/agentic-ai-chip-design-blog-thumb-3?ts=1790788778468&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Learn why domain expertise and company knowledge are becoming critical advantages for agentic AI in semiconductor design.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/agentic-ai-design-knowledge.html"> Agentic AI in Chip Design: Why Knowledge Becomes the Advantage (Part 3 of 4)</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Agentic AI in Chip Design: The Rise of Autonomous Engineering (Part 2 of 4)</title>
<link>https://www.synopsys.com/blogs/chip-design/agentic-ai-autonomous-engineering.html</link>
<dc:creator><![CDATA[Thomas Andersen]]></dc:creator>
<pubDate>Thu, 17 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/agentic-ai-autonomous-engineering.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/agentic-ai-chip-design-blog-thumb-4?ts=1790787265610&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Discover how agentic AI is evolving from assistance to autonomous engineering with goal-directed workflows across chip design.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/agentic-ai-autonomous-engineering.html"> Agentic AI in Chip Design: The Rise of Autonomous Engineering (Part 2 of 4)</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>The Commercial Case for Quantum Computing Is Taking Shape</title>
<link>https://www.synopsys.com/blogs/chip-design/quantum-computing-commercialization.html</link>
<dc:creator><![CDATA[Prith Banerjee]]></dc:creator>
<pubDate>Thu, 17 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["Quantum Computing"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/quantum-computing-commercialization.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/quantum-computing-cfd-fea-image-400x225-1?ts=1789664872042&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Explore quantum computing commercialization through hybrid workflows that delivered up to 14.6% end-to-end FEA gains on large industrial models.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/quantum-computing-commercialization.html"> The Commercial Case for Quantum Computing Is Taking Shape</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Agentic AI in Chip Design: Hitting the Capacity Wall (Part 1 of 4)</title>
<link>https://www.synopsys.com/blogs/chip-design/agentic-ai-chip-design-capacity.html</link>
<dc:creator><![CDATA[Thomas Andersen]]></dc:creator>
<pubDate>Tue, 15 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/agentic-ai-chip-design-capacity.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/agentic-ai-chip-design-blog-thumb-2?ts=1790786350310&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Rising chip complexity is outpacing engineering capacity. Learn why agentic AI may be key to scaling semiconductor innovation.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/agentic-ai-chip-design-capacity.html"> Agentic AI in Chip Design: Hitting the Capacity Wall (Part 1 of 4)</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Agentic AI in Chip Design: Four-Part Executive Series</title>
<link>https://www.synopsys.com/blogs/chip-design/agentic-ai-chip-design-series.html</link>
<dc:creator><![CDATA[Thomas Andersen]]></dc:creator>
<pubDate>Tue, 15 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/agentic-ai-chip-design-series.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/agentic-ai-chip-design-spotlight-image-thumb?ts=1791238581475&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Explore how agentic AI can scale chip design through autonomous engineering, operationalized expertise, and human orchestration.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/agentic-ai-chip-design-series.html"> Agentic AI in Chip Design: Four-Part Executive Series</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Synopsys Joins Arm Total Design for Physical AI to Advance Autonomous Systems</title>
<link>https://www.synopsys.com/blogs/chip-design/arm-total-design-physical-ai.html</link>
<dc:creator><![CDATA[Arun Bhattacharya, Sumit Vishwakarma]]></dc:creator>
<pubDate>Wed, 9 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Silicon IP"]]></category>
<category><![CDATA["Verification"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/arm-total-design-physical-ai.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/physical-ai-autonomous-warehouse-robot-image_400x225?ts=1789406150376&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Learn how Synopsys and Arm Total Design help accelerate Physical AI systems with pre-validated IP, virtual development, and system-level design.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/arm-total-design-physical-ai.html"> Synopsys Joins Arm Total Design for Physical AI to Advance Autonomous Systems</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Energy-Efficient AI: How the Silicon Industry Is Engineering More Intelligence Out of Every Watt</title>
<link>https://www.synopsys.com/blogs/chip-design/energy-efficient-ai-per-watt.html</link>
<dc:creator><![CDATA[Greg Sorber]]></dc:creator>
<pubDate>Wed, 2 Sep 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Energy-Efficient SoCs"]]></category>
<category><![CDATA["Design Technology Co-Optimization"]]></category>
<category><![CDATA["HPC, Data Center"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/energy-efficient-ai-per-watt.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/ai-data-center-energy-efficiency-electricity-meter-image-400x225?ts=1788296260596&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Learn how industry leaders are improving AI energy efficiency through full-stack co-design, advanced packaging, and AI-driven chip design.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/energy-efficient-ai-per-watt.html"> Energy-Efficient AI: How the Silicon Industry Is Engineering More Intelligence Out of Every Watt</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>India&#8217;s Semiconductor Ecosystem is Moving from Participation to Influence</title>
<link>https://www.synopsys.com/blogs/chip-design/india-semiconductor-industry-influence.html</link>
<dc:creator><![CDATA[Sudeep Shivalli]]></dc:creator>
<pubDate>Tue, 25 Aug 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["Aerospace & Government"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/india-semiconductor-industry-influence.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/india-semiconductor-ecosystem-bangalore-skyline-400x225?ts=1787769695465&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>India’s semiconductor ecosystem is evolving through innovation, investment, and collaboration, positioning the country for greater global influence.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/india-semiconductor-industry-influence.html"> India&#8217;s Semiconductor Ecosystem is Moving from Participation to Influence</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>HPE: Accelerating High-Performance Computing Through Smarter Tools and Collaboration</title>
<link>https://www.synopsys.com/blogs/chip-design/hpe-hpc-chip-design-tools.html</link>
<dc:creator><![CDATA[Wim Slagter]]></dc:creator>
<pubDate>Wed, 12 Aug 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Cloud"]]></category>
<category><![CDATA["HPC, Data Center"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/hpe-hpc-chip-design-tools.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/hpe-hpc-board-heatsink-image-400x225?ts=1786635886239&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Learn how HPE boosts HPC chip development with Synopsys tools, elastic compute resources, streamlined verification, and AI-driven workflows.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/hpe-hpc-chip-design-tools.html"> HPE: Accelerating High-Performance Computing Through Smarter Tools and Collaboration</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Creating a Digital Twin of the Moon</title>
<link>https://www.synopsys.com/blogs/chip-design/rf-digital-twin-of-the-moon.html</link>
<dc:creator><![CDATA[Shawn Carpenter]]></dc:creator>
<pubDate>Tue, 4 Aug 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Aerospace & Government"]]></category>
<category><![CDATA["RF Design"]]></category>
<category><![CDATA["Verification"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/rf-digital-twin-of-the-moon.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/digital-twin-moon-synopsys-ansys-image-400x225?ts=1785859360499&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Discover how a lunar RF digital twin helps model wireless coverage, validate antennas, and reduce communications risks for Artemis missions.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/rf-digital-twin-of-the-moon.html"> Creating a Digital Twin of the Moon</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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<title>Multi-Die, Multiphysics, and the New Rules of Chip Design</title>
<link>https://www.synopsys.com/blogs/chip-design/multi-die-multiphysics-co-design.html</link>
<dc:creator><![CDATA[Greg Sorber]]></dc:creator>
<pubDate>Wed, 29 Jul 2026 07:00:00 +0000</pubDate>
<category><![CDATA["About Synopsys"]]></category>
<category><![CDATA["Executive Voices"]]></category>
<category><![CDATA["AI & Machine Learning"]]></category>
<category><![CDATA["Multi-Die"]]></category>
<category><![CDATA["Verification"]]></category>
<category><![CDATA["Design"]]></category>
<guid isPermaLink="false">https://www.synopsys.com/blogs/chip-design/multi-die-multiphysics-co-design.html</guid>
<description><![CDATA[ <div><img width="300" height="169" src="https://images.synopsys.com/is/image/synopsys/multi-die-panel-synopsys-executive-forum-400x225?ts=1787683192975&$responsive$" alt="" loading="lazy" style="margin-bottom: 10px;" /></div> <p>Learn how multi-die architectures are driving multiphysics analysis, co-design workflows, AI-driven exploration, and next-generation chip innovation.</p><p>The post <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design/multi-die-multiphysics-co-design.html"> Multi-Die, Multiphysics, and the New Rules of Chip Design</a> appeared first on <a rel="nofollow" href="https://www.synopsys.com/blogs/chip-design.html"> Chip Design</a>.</p> ]]></description>
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