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Physical AI Is Moving from Lab to Market

By Sumit Vishwakarma

Tags: Customer Spotlight, AI & Machine Learning, Simulation, Design, About Synopsys, Verification

BLOG Aug 04, 2026/5 min read

BLOG

Creating a Digital Twin of the Moon

By Shawn Carpenter

Tags: Aerospace & Government, RF Design, Simulation, Design, About Synopsys, Verification

BLOG Apr 02, 2026/4 min read

BLOG

Volvo Cars’ Digital Twin Advantage

By Marin Stanev

Tags: Customer Spotlight, Cloud, Simulation, Design, About Synopsys, Automotive, Verification, Virtual Prototyping

AI-Driven Accelerated Bug Discovery and Coverage Closure

BLOG Mar 18, 2026/4 min read

BLOG

AI-Driven Accelerated Bug Discovery and Coverage Closure

By Taruna Reddy

Tags: Engineering Central, AI & Machine Learning, Simulation, Verification

New Fujitsu Chip to Power Greener, Smarter Data Centers

BLOG Dec 02, 2025/4 min read

BLOG

New Fujitsu Chip to Power Greener, Smarter Data Centers

By Greg Sorber

Tags: Multi-Die, Debug, Simulation, 3DIC Design, Emulation, About Synopsys, Energy-Efficient SoCs, Customer Spotlight, Data Center, Design, 5nm and Below, HPC, Data Center, Verification

AI Chips: Why Pre-Silicon Planning Is Critical

BLOG Oct 14, 2025/3 min read

BLOG

AI Chips: Why Pre-Silicon Planning Is Critical

By Scott Knowlton, Kamal Desai, Sumit Vishwakarma

Tags: Multi-Die, AI & Machine Learning, Signal & Power Integrity, Simulation, Design, About Synopsys, Interface IP, Energy-Efficient SoCs, Foundation IP, Silicon IP, Verification, Virtual Prototyping

Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow

BLOG Oct 07, 2025/5 min read

BLOG

Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow

By Frank Schirrmeister

Tags: AI & Machine Learning, Debug, Prototyping, Simulation, Emulation, About Synopsys, Interface IP, Energy-Efficient SoCs, Foundation IP, Interface IP Subsystems, Verification IP, Virtual Prototyping, Silicon Lifecycle Management, Signal & Power Integrity, Design, Security IP, HPC, Data Center, Silicon IP, Verification

Hybrid Cloud for Chip Design: Agility, Cost Efficiency, and Data Continuity

BLOG Sep 24, 2025/5 min read

BLOG

Hybrid Cloud for Chip Design: Agility, Cost Efficiency, and Data Continuity

By Xingang Zhao, Varun Shah

Tags: Cloud, AI & Machine Learning, Insights, Simulation, Design, About Synopsys, Signoff, Verification

A Beginner’s Guide to Chiplets: 8 Best Practices for Multi-Die Designs

BLOG Aug 26, 2025/4 min read

BLOG

A Beginner’s Guide to Chiplets: 8 Best Practices for Multi-Die Designs

By Rob Kruger

Tags: Multi-Die, AI & Machine Learning, Simulation, Design, About Synopsys, Interface IP, Foundation IP, Interface IP Subsystems, HPC, Data Center, Silicon IP, Verification

Quantum Computing: How Advances May Reshape Our Understanding of the World

BLOG Jul 29, 2025/4 min read

BLOG

Quantum Computing: How Advances May Reshape Our Understanding of the World

By Greg Sorber

Tags: Executive Voices, Test, Quantum Computing, Simulation, Design, About Synopsys, Verification

Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development

BLOG Jul 15, 2025/4 min read

BLOG

Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development

By Greg Sorber

Tags: Executive Voices, Simulation, Design, About Synopsys, Automotive, Verification, Virtual Prototyping

Driving the Future of Automotive: How Synopsys and Tata Elxsi Are Powering Electronics Digital Twin (eDT) Adoption

BLOG Jul 11, 2025/2 min read

BLOG

Driving the Future of Automotive: How Synopsys and Tata Elxsi Are Powering Electronics Digital Twin (eDT) Adoption

By Chahinez Hamlaoui, Marc Serughetti

Tags: Test, Simulation, Design, About Synopsys, Automotive, Verification, Virtual Prototyping

RTL Signoff vs. Functional Signoff: What’s the Difference?

BLOG Jul 01, 2025/5 min read

BLOG

RTL Signoff vs. Functional Signoff: What’s the Difference?

By Bradley Geden, Manoz Palaparthi

Tags: Multi-Die, RTL Synthesis, Static & Formal Verification, AI & Machine Learning, Debug, Physical Verification, Test, Simulation, About Synopsys, Energy-Efficient SoCs, Signoff, Design, Verification, Formal Verification

Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

BLOG Apr 04, 2025/3 min read

BLOG

Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

By Taruna Reddy

Tags: AI & Machine Learning, Debug, Simulation, Verification IP, Verification

Synopsys HAPS-200 and ZeBu-200 Expand the Industry’s Highest Performance Hardware-Assisted Verification Portfolio

BLOG Feb 13, 2025/5 min read

BLOG

Synopsys HAPS-200 and ZeBu-200 Expand the Industry’s Highest Performance Hardware-Assisted Verification Portfolio

By Frank Schirrmeister

Tags: Simulation, Design, Emulation, About Synopsys, Verification, Virtual Prototyping

BLOG Sep 10, 2024/2 min read

BLOG

The Journey of Coverage Closure

By Taruna Reddy

Tags: Engineering Central, AI & Machine Learning, Simulation, Verification

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

BLOG May 09, 2024/3 min read

BLOG

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

By Vita Liao

Tags: Engineering Central, Debug, Simulation, Verification

Running X-Propagation with Low-Power Simulation

BLOG Nov 21, 2023/5 min read

BLOG

Running X-Propagation with Low-Power Simulation

By Manas Ranjan Raiguru

Tags: Engineering Central, Simulation, Verification

Streamline Projects with Verdi and VCS Coverage Tools

BLOG Jul 12, 2023/2 min read

BLOG

Streamline Projects with Verdi and VCS Coverage Tools

By Taruna Reddy

Tags: Engineering Central, Debug, Simulation, Verification, Formal Verification

How Imparé Leverages Chip Design Verification in the Cloud

BLOG May 03, 2023/6 min read

BLOG

How Imparé Leverages Chip Design Verification in the Cloud

By Rob van Blommestein

Tags: Customer Spotlight, Cloud, Debug, Simulation, About Synopsys, Blog, Verification

How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud

BLOG Mar 07, 2023/6 min read

BLOG

How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud

By Meghana Bellumori

Tags: Cloud, Simulation, About Synopsys, Blog, Verification

Enhancing Chip Design Simulation with AI

BLOG Feb 15, 2023/4 min read

BLOG

Enhancing Chip Design Simulation with AI

By Taruna Reddy

Tags: AI & Machine Learning, Debug, Simulation, About Synopsys, Blog, Verification

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

BLOG Dec 15, 2022/2 min read

BLOG

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

By Taruna Reddy

Tags: Engineering Central, Debug, Simulation, Verification

How Formal Verification Tools Enhance SoC Simulation Coverage

BLOG Nov 20, 2022/4 min read

BLOG

How Formal Verification Tools Enhance SoC Simulation Coverage

By Jin Zhang

Tags: Simulation, About Synopsys, Blog, Verification, Formal Verification

How to Protect Advanced Chip Designs from Security Breaches

BLOG Nov 09, 2022/5 min read

BLOG

How to Protect Advanced Chip Designs from Security Breaches

By Ian Land

Tags: Aerospace & Government, Silicon Lifecycle Management, Prototyping, Simulation, Design, Emulation, About Synopsys, Blog, Silicon IP, Verification, Formal Verification

BLOG Sep 04, 2022/1 min read

BLOG

Synopsys VCS and VIP By-the-Minute

By Verification Expert

Tags: Cloud, Engineering Central, Simulation, Verification IP, Verification

Enhancing Chip Verification with AI and Machine Learning

BLOG Jul 12, 2022/4 min read

BLOG

Enhancing Chip Verification with AI and Machine Learning

By Rob van Blommestein

Tags: Multi-Die, Static Verification, AI & Machine Learning, Debug, Simulation, About Synopsys, HPC, Data Center, Blog, Verification, Formal Verification

Fault Simulation Techniques for Growing Chip Complexity

BLOG Jun 01, 2022/6 min read

BLOG

Fault Simulation Techniques for Growing Chip Complexity

By Brian Davenport, Rimpy Chugh

Tags: Customer Spotlight, Aerospace & Government, Debug, Simulation, About Synopsys, Automotive, Blog, Verification

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

BLOG Mar 20, 2022/4 min read

BLOG

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

By Ramesh Narayanaswamy

Tags: Customer Spotlight, Debug, Simulation, About Synopsys, Blog, Verification

What is Clock Domain Crossing? - ASIC Design Challenges

BLOG Nov 22, 2021/7 min read

BLOG

What is Clock Domain Crossing? - ASIC Design Challenges

By Rimpy Chugh

Tags: Debug, Simulation, About Synopsys, Blog, Verification

Software-Enabled Full Chip Power Signoff & SoC Verification

BLOG Nov 03, 2021/5 min read

BLOG

Software-Enabled Full Chip Power Signoff & SoC Verification

By Godwin Maben

Tags: Simulation, Emulation, About Synopsys, Energy-Efficient SoCs, Blog, Verification

How Emulation Helps Find Power Bugs During SoC Verification

BLOG Jul 06, 2021/5 min read

BLOG

How Emulation Helps Find Power Bugs During SoC Verification

By Alex Wakefield

Tags: Static Verification, Simulation, Design, Emulation, About Synopsys, Energy-Efficient SoCs, Signoff, Blog, Verification, Virtual Prototyping, Formal Verification

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NOTICE: You are interacting with an AI-powered chatbot that provides general information about Synopsys, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by Synopsys and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.

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Browse by Tags

Physical AI Is Moving from Lab to Market

Creating a Digital Twin of the Moon

Volvo Cars’ Digital Twin Advantage

AI-Driven Accelerated Bug Discovery and Coverage Closure

New Fujitsu Chip to Power Greener, Smarter Data Centers

AI Chips: Why Pre-Silicon Planning Is Critical

Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow

Hybrid Cloud for Chip Design: Agility, Cost Efficiency, and Data Continuity

A Beginner’s Guide to Chiplets: 8 Best Practices for Multi-Die Designs

Quantum Computing: How Advances May Reshape Our Understanding of the World

Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development

Driving the Future of Automotive: How Synopsys and Tata Elxsi Are Powering Electronics Digital Twin (eDT) Adoption

RTL Signoff vs. Functional Signoff: What’s the Difference?

Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

Synopsys HAPS-200 and ZeBu-200 Expand the Industry’s Highest Performance Hardware-Assisted Verification Portfolio

The Journey of Coverage Closure

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

Running X-Propagation with Low-Power Simulation

Streamline Projects with Verdi and VCS Coverage Tools

How Imparé Leverages Chip Design Verification in the Cloud

How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud

Enhancing Chip Design Simulation with AI

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

How Formal Verification Tools Enhance SoC Simulation Coverage

How to Protect Advanced Chip Designs from Security Breaches

Synopsys VCS and VIP By-the-Minute

Enhancing Chip Verification with AI and Machine Learning

Fault Simulation Techniques for Growing Chip Complexity

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

What is Clock Domain Crossing? - ASIC Design Challenges

Software-Enabled Full Chip Power Signoff & SoC Verification

How Emulation Helps Find Power Bugs During SoC Verification

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