VCS HyperSim: Hyper-Scaling SoC Verification to Accelerate Chip Tape-Out

Functional design verification is one of the biggest challenges in semiconductor development, often consuming 60-70% of total effort in modern system-on-chip (SoC) projects. As designs grow into the multi-billion-gate range and simulation regressions stretch into days, verification turnaround time has become the single greatest determinant of tape-out risk and time-to-market (TTM).

Even when the best methodologies are used there’s never enough time to run all the desired simulation tests. Anything that speeds up your per-simulation performance enables more thorough verification in the available time, reduces compute costs, shortens TTM, and increases your chance of first-silicon success. This blog post describes how Synopsys VCS HyperSim provides just such a solution.

Competitive pressures affect every aspect of chip development. Most companies face stiff competition to win over end users. Being one of the first to market is often a tremendous advantage, but this puts pressure on the development team to tape out a working chip as quickly as possible. Verification is squarely in the middle of this process. In addition, rapidly evolving markets mean that product lifetime is shrinking at the same time as development cycles contract.

As if this business challenge wasn’t enough, verification teams also face technical hurdles. For a start, design complexity has outpaced simulator throughput. Single-core simulation performance has largely plateaued, while SoC gate counts continue to double. Compute systems with multiple cores are now commonplace, and many phases of the chip development flow have been able to leverage these by parallel processing.

Unfortunately, functional simulation has historically achieved very little speed-up on multi-core servers. Adding more servers to the farm increases project-level throughout, but compute budgets are finite, so this provides only limited relief. Adding more cores may be less expensive but, unless simulation can scale for more parallelism, the verification team is just paying for idle silicon.

Simulation-based verification is based on regressions, where a large set of tests is run every time that the design changes. Regression windows are fixed by business schedules, not by engineering preference. When a regression run takes more than a few hours, engineers get only one iteration per day. Any errors found must be debugged and fixed, and any coverage holes identified must be plugged by additional tests. Daily regression runs set a hard ceiling on the pace of verification closure.

VCS HyperSim is a production-proven, multi-core technology that transparently parallelizes a single simulation across any number of CPU cores, typically 4, 8, 12, or 16. Unlike farm-level parallelism, which only scales how many simulations run concurrently, VCS HyperSim accelerates your critical-path simulation tests, reducing the time for each test and thereby each regression run. This means that each incremental bug fix and coverage improvement step is much faster.

VCS HyperSim is fully integrated into the Synopsys VCS flow. Your teams continue to use the same compiler, the same UVM testbench, the same debug tools (Synopsys Verdi), and the same regression infrastructure. Adoption requires only adding a HyperSim option to the existing VCS compile and run commands. There is no methodology change, no RTL design rewrite, and no testbench partitioning.

VCS HyperSim complements, rather than replaces, the Synopsys verification portfolio:

• Regression scale-out is still handled by the existing compute grid (LSF, Netbatch, or SLURM)
• Compile-time acceleration is addressed by the Synopsys Next-Generation Parallel Compiler and Distributed Compilation
• Coverage, debug, assertions, low-power, AMS, and UVM all continue to operate normally—but faster

VCS HyperSim slots cleanly into this portfiolio to attack your verification key bottleneck: runtime of the longest simulations.

Synopsys customers are deploying VCS HyperSim on large scale, high-activity designs such as CPU cores, GPUs, AI/ML accelerators, networking chips, and large SoC integrations. They typically report:

• Significant wall-clock speed-up on long-running RTL, full-SoC, and zero-delay gate-level (functional and DFT) simulations, scaling with available cores
• Reduced regression duration, often transforming overnight runs into same-day runs
• Improved engineer utilization, because faster turnaround enables more iterations per day
• Better compute ROI, converting idle cores on already-purchased servers into verification throughput

A built-in Design Suitability Diagnostic allows your teams to measure the expected benefit of VCS HyperSim benefit on your own design, with projections at typical core counts, before committing to full deployment. This diagnostic produces two equally valuable outcomes. If the projected gain is acceptable, VCS HyperSim runs out of the box on your design, with no further engineering investment is required.

If the projected gain is not yet acceptable, the same diagnostic explains why (testbench-bound, low time-per-cycle, blocking events, etc.) and points to the specific testbench and RTL code that hinders the parallel gain. This two-path outcome is unique to VCS HyperSim. You do not just find out whether parallel simulation works for you today; you learn exactly what it would take to make it work, in priority order. There are no surprises and no wasted pilot projects.

Once you determine the projected gains, you can scope a pilot project in a matter of weeks. Moving from the pilot project to full adoption is incremental; your teams can opt in design-by-design and mode-by-mode. No RTL, testbench, or flow rewrite is required if the design is already suitable. Your Synopsys Applications Engineer (AE) provides a built-in profiling and bring-up methodology, documented and supported, so your team can validate projected speed-up on representative workloads before broadening deployment.

1. Identify your two longest-running regressions
2. Request a VCS HyperSim Design Suitability assessment from your Synopsys AE
3. Pilot on one project through a tape-out cycle
4. Measure wall-clock reduction, engineer iteration rate, and compute utilization
5. Scale across your design teams

Verification runtime is no longer a technical constraint you must accept—it is a business lever you can pull. VCS HyperSim directly targets your per-simulation performance ceiling. It is the only technology that can apply multiple CPUs to a single long-running simulation without any change to your design or testbench methodology. VCS HyperSim converts already-purchased server cores into additional verification throughput for a meaningful reduction in compute cost per verified cycle. It shortens the time between a bug report and a bug fix, accelerates coverage closure, and restores schedule predictability to the most uncertain phase of modern SoC development.

For organizations where a lost week in verification equals a missed market window, VCS HyperSim is no longer an optimization. It is a competitive necessity.