Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Platform Architect™ provides architects and system designers with SystemC™ TLM-based tools and efficient methods for early analysis and optimization of multicore SoC architectures for performance and power. To accelerate architecture design, also take advantage of the Architecture Design Models, and CoStart Enablement Services.
Its efficient turnaround time, powerful analysis views, and available models make Platform Architect the premier choice for system-level analysis and optimization of complex SoCs and multi-SoC designs. Platform Architect is a production-proven solution for embedded systems architecture used by leading systems OEMs and semiconductor companies worldwide.
Supporting all flows for early Architecture Design
Workloads to different SoC architectures to resolve AI design challenges
Hardware-Software Partitioning and Optimization of Multicore Systems
SoC Interconnect and Memory Subsystem Performance and Power Optimization
Using Traffic Generation & Cycle-Accurate TLM Interconnect Models
Of Activity, Performance, and Power for Root-Cause Analysis
With Parameter Sweeing and Sensitivity Analysis
Using Cycle-Accurate TLM Processor Models
IEEE 1666-2011 SystemC TLM-2.0 Standards-based Environment
Quickly address challenges of evolving algorithms, highly parallel compute and high memory requirements with Platform Architect
Platform Architect enables architects to create task-driven workload models of their end-product application for early architecture analysis.
Trace-driven traffic generation enables architects to focus on the challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem.
After exploration the model of the candidate architecture can be refined to replace the trace-driven and task-driven traffic generators with cycle-accurate processor models.
Complete IEEE 1666-2011SystemC TLM-2.0 Standards-based Environment
Synopsys Platform Architect is a native SystemC environment fully compatible with the IEEE 1666-2011 SystemC TLM-2.0 Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of abstraction including:
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