Platform Architect MCO

Hardware-Software Partitioning and Optimization of Multicore Systems
Platform Architect with Multicore Optimization Technology enables architects to create task-driven workload models of their end-product application for early architecture analysis.

• Generic task models are easily configured to create a SystemC performance model of the application, called a task-graph
• Using the task-graph, the performance workload of parallel application tasks are mapped onto Virtual Processing Unit (VPU) task-driven traffic generators
• Simulation and task analysis enables hardware-software partitioning to be optimized for best system performance well before the application software is available
• Task graphs are fully reusable as task-driven traffic generators for Interconnect and Memory Subsystem Performance Optimization in combination trace-driven traffic generation

Interconnect and Memory Subsystem Performance Optimization Using Trace-Driven Traffic Generation
Trace-driven traffic generation enables architects to focus on the challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem.

• Dynamic application workloads are modeled using traffic generation, enabling early measurement of system performance and power before software is available
• Simulation sweeping enables analysis data to be collected parametrically, exploring all traffic scenarios against the complete of range architecture configurations
• Powerful tools for analysis visualization provide graphical transaction tracing and statistical analysis views that enable you to identify bottlenecks, determine their root-cause and examine the sensitivity that system performance and power may have to individual or combined parameter settings
• The result is an executable specification used to carefully dimension the SoC interconnect and memory subsystem to support the latency, bandwidth, and power requirements of all SoC components, under all operating conditions

Hardware-Software Performance Validation Using Processors Models and Critical Software 
After exploration the model of the candidate architecture can be refined to replace the trace-driven and task-driven traffic generators with cycle-accurate processor models.

• This enables architects to validate the candidate architecture using the available performance critical software
• Software and hardware analysis views can be visualized together to provide unique system-level visibility to measure performance and power and confirm goals are met