Cloud native EDA tools & pre-optimized hardware platforms
Dynamic simulation is needed. Traditional RTL simulation is too slow and lacks the configurability and visibility to analyze performance. In addition, the RTL may simply not be available. Risks include over-design, under-design, cost increases, schedule delays and re-spins.
Synopsys Platform Architect™ provides architects and system designers with SystemC™ TLM-based tools and efficient methods for early analysis and optimization of multicore SoC architectures for performance and power. To accelerate architecture design, also take advantage of the Architecture Design Models, and CoStart Enablement Services.
Highlights
Synopsys Platform Architect is a SystemC TLM standards-based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance and power of multicore systems and next-generation SoC architectures. Platform Architect enables system designers to explore and optimize the hardware-software partitioning and the configuration of the SoC infrastructure, specifically the global interconnect and memory subsystem, to achieve the right system performance, power, and cost.
Its efficient turnaround time, powerful analysis views, and available models make Platform Architect the premier choice for system-level analysis and optimization of complex SoCs and multi-SoC designs. Platform Architect is a production-proven solution for embedded systems architecture used by leading systems OEMs and semiconductor companies worldwide.
Easily Map AI Workloads to Different SoC Architectures to Resolve AI Power and Performance Design Challenges
Quickly address challenges of evolving algorithms, highly parallel compute and high memory requirements with Platform Architect
Hardware-Software Partitioning and Optimization of Multicore Systems
Platform Architect enables architects to create task-driven workload models of their end-product application for early architecture analysis.
Interconnect and Memory Subsystem Performance Optimization Using Trace-Driven Traffic Generation
Trace-driven traffic generation enables architects to focus on the challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem.
Hardware-Software Performance Validation Using Processors Models and Critical Software
After exploration the model of the candidate architecture can be refined to replace the trace-driven and task-driven traffic generators with cycle-accurate processor models.
Application task analysis for early optimization of multicore systems
Model debugging using TLM port transaction trace
Root cause analysis using bus path and resource utilization statistics
Combining HW/SW analysis for architecture validation
Sensitivity analysis using pivot charts to aggregate and explore results
Complete IEEE 1666-2011SystemC TLM-2.0 Standards-based Environment
Synopsys Platform Architect is a native SystemC environment fully compatible with the IEEE 1666-2011 SystemC TLM-2.0 Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of abstraction including: