Mastering AI Chip Complexity
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SoC Architecture Analysis and Optimization for Performance and Power
Synopsys Platform Architect™ is a SystemC™ standards-based performance and power analysis tool for early SoC architecture exploration and design. Using transaction-level simulation , it reduces design time by predicting and optimizing architecture KPIs.
Platform Architect helps optimize hardware-software partitioning, IP selection and configuration, interconnect and memory configuration, and power.
Today’s SoC complexity means spreadsheet-based architecture tools are inefficient and run a high risk of re-spins to meet power and performance targets, resulting in higher costs and TTM delay. With the largest library of architecture models, and fast capture of task and trace-based SW workloads, Platform Architect is the choice to shift-left your architecture design and deliver the right product on schedule.
In addition, Synopsys Platform Architect for Multi-Die Systems accounts for the interdependencies between multiple dies, or chiplets, within multi-die systems.
Key Benefits
Features
- Largest library of transaction-level performance models
- Fastest capture of task and trace-based SW workloads
- Application specific support (AI, automotive, networking)
- System level power analysis based on IEEE-1801 UPF power monitors
- Intuitive analysis of tradeoffs and KPIs
- Fast design space sweeping and sensitivity analysis
- Easy to use UI to dynamically model, simulate, and analyze SoC architecture designs
- Command line interface for automated execution of architecture development tasks
- IEEE-1666 SystemC standards-based simulation environment
- Role-based access with Platform Architect Development Kit for collaborative simulation and analysis
What's New
What Our Customers Are Saying
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Resources
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White Paper
Turbo-Charging Continuous Integration and Development Flows with Virtual Prototypes
Video
Platform Architect Demonstration Running on ARC® NPX NPU Processor IP
Explore on-demand presentations from our annual Virtual Prototyping Day
Arteris - Performance Analysis for Network-on-Chip Development Using Synopsys Platform Architect
Infineon - Using Platform Architect for Architecting the Next Generation AURIX Microcontrollers
Intel - Optimizing SoC Performance for Networking Workloads: Fabric, System Cache, and DRAM
Kalray - Interconnect and Memory Performance Exploration of Many-Core SoCs
Microsoft - Pre-Design Verification and Optimization for On-chip Interconnects
ST - NoC Design and Platform Integration for Early Benchmarking of Automotive Processor SoCs
Synopsys - Benefits of Early Architecture Design for Multi-Die Systems
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