About Platform Architect

Synopsys Platform Architect™ is a SystemC™ standards-based performance and power analysis tool for early SoC architecture exploration and design. Using transaction-level simulation , it reduces design time by predicting and optimizing architecture KPIs. ​

Platform Architect helps optimize hardware-software partitioning, IP selection and configuration, interconnect and memory configuration, and power. ​

Today’s SoC complexity means spreadsheet-based architecture tools are inefficient and run a high risk of re-spins to meet power and performance targets, resulting in higher costs and TTM delay.  With the largest library of architecture models, and fast capture of task and trace-based SW workloads, Platform Architect is the choice to shift-left your architecture design and deliver the right product on schedule.

In addition, Synopsys Platform Architect for Multi-Die Systems accounts for the interdependencies between multiple dies, or chiplets, within multi-die systems.

Key Benefits

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Partitioning & Optimization

Hardware-Software Partitioning and Optimization of Multicore Systems

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Power Optimization

SoC Interconnect and Memory Subsystem Performance and Power Optimization

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Efficient Exploration

Using Traffic Generation & Cycle-Accurate TLM Interconnect Models

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Unified View

Of Activity, Performance, and Power for Root-Cause Analysis


  • Largest library of transaction-level architecture models​
  •  Fastest capture of task and trace-based SW workloads​
  •  Application specific support (AI, automotive, networking)​
  •  System level power analysis based on IEEE-1801 UPF power monitors​
  •  Intuitive analysis of tradeoffs and KPIs​
  •  Fast design space sweeping and sensitivity analysis​
  •  Easy to use UI to dynamically model, simulate, and analyze SoC architecture designs​
  •  Command line interface for automated execution of architecture development tasks​
  •  IEEE-1666 SystemC standards-based simulation environment


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