Platform Architect

SoC Architecture Analysis and Optimization for Performance and Power

While spreadsheets are good for aggregating data, static spreadsheet calculations are not accurate enough to estimate performance and power and make design decisions.

Dynamic simulation is needed. Traditional RTL simulation is too slow and lacks the configurability and visibility to analyze performance. In addition, the RTL may simply not be available. Risks include over-design, under-design, cost increases, schedule delays and re-spins.

Synopsys Platform Architect™ provides architects and system designers with SystemC™ TLM-based tools and efficient methods for early analysis and optimization of multicore SoC architectures for performance and power. To accelerate architecture design, also take advantage of the Architecture Design Models, and CoStart Enablement Services.

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Platform Architect

Highlights

Integrated graphical environment supporting all flows for early Architecture Design, including Workload and Hardware Modeling, Architecture Mapping, Parallel Sweeping, and Analysis
Easily map artificial intelligence (AI) workloads to different SoC architectures to resolve AI design challenges
Hardware-Software Partitioning and Optimization of Multicore Systems
SoC Interconnect and Memory Subsystem Performance and Power Optimization
Efficient Exploration Using Traffic Generation & Cycle-Accurate TLM Interconnect Models
Unified View of Activity, Performance, and Power for Root-Cause Analysis
Systematic Design Space Exploration with Parameter Sweeing and Sensitivity Analysis
Hardware-Software Validation Using Cycle-Accurate TLM Processor Models
IEEE 1666-2011 SystemC TLM-2.0 Standards-based Environment

Synopsys Platform Architect is a SystemC TLM standards-based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance and power of multicore systems and next-generation SoC architectures. Platform Architect enables system designers to explore and optimize the hardware-software partitioning and the configuration of the SoC infrastructure, specifically the global interconnect and memory subsystem, to achieve the right system performance, power, and cost.

Its efficient turnaround time, powerful analysis views, and available models make Platform Architect the premier choice for system-level analysis and optimization of complex SoCs and multi-SoC designs. Platform Architect is a production-proven solution for embedded systems architecture used by leading systems OEMs and semiconductor companies worldwide.

Analysis and Optimization

Easily Map AI Workloads to Different SoC Architectures to Resolve AI Power and Performance Design Challenges

Quickly address challenges of evolving algorithms, highly parallel compute and high memory requirements with Platform Architect

Automated generation of workloads from AI frameworks, including an AI operator library for Convolutional Neural Network (CNN) modeling
AI centric HW architecture model library consisting of Virtual Processing Units (VPUs) with specific parameters to represent AI compute and DMA engines, relevant interconnect and memory subsystem models, and example NVDLA performance models to rapidly represent custom AI accelerators
AI specific analysis views to determine memory and processing rooflines

Hardware-Software Partitioning and Optimization of Multicore Systems
Platform Architect enables architects to create task-driven workload models of their end-product application for early architecture analysis.

Generic task models are easily configured to create a hierarchical workload model of the application, called a task-graph
The application workload model is mapped onto a model of the hardware platform, based on Virtual Processing Units (VPUs) and other system TLM performance models from the rich Platform Architect model library
Platform and workload analysis enable hardware-software partitioning to be optimized for best system performance well before the application software is available
Task graphs are fully reusable as elastic task-driven traffic generators for Interconnect and Memory Subsystem Performance Optimization

Interconnect and Memory Subsystem Performance Optimization Using Trace-Driven Traffic Generation
Trace-driven traffic generation enables architects to focus on the challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem.

Dynamic application workloads are modeled using traffic generation, enabling early measurement of system performance and power before software is available
Simulation sweeping enables parametric collection of analysis data, exploring all workload scenarios against a range of architecture configurations
Powerful tools for analysis visualization provide graphical transaction tracing and statistical analysis views that enable you to identify bottlenecks, determine their root-cause and examine the sensitivity that system performance and power may have to individual or combined parameter settings
The result is an executable specification used to carefully dimension the SoC interconnect and memory subsystem to support the latency, bandwidth, and power requirements of all SoC components, under all operating conditions

Hardware-Software Performance Validation Using Processors Models and Critical Software
After exploration the model of the candidate architecture can be refined to replace the trace-driven and task-driven traffic generators with cycle-accurate processor models.

This enables architects to validate the candidate architecture using the available performance critical software
Software and hardware analysis views can be visualized together to provide unique system-level visibility to measure performance and power and confirm goals are met

Application task analysis for early optimization of multicore systems

Model debugging using TLM port transaction trace

Sensitivity Analysis using pivot charts to aggregate and explore results

Root cause analysis using bus path and resource utilization statistics

Root Cause Analaysis using bus path and resource and utilization statistics

Combining HW/SW analysis for architecture validation

Sensitivity analysis using pivot charts to aggregate and explore results

SystemC

Complete IEEE 1666-2011SystemC TLM-2.0 Standards-based Environment
Synopsys Platform Architect is a native SystemC environment fully compatible with the IEEE 1666-2011 SystemC TLM-2.0 Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of abstraction including:

SystemC transaction-level models using IEEE 1666-2011 TLM-2.0 and Accellera Systems Initiative (ASI) TLM industry standards, and the open Synopsys SystemC Modeling Library (SCML) API library for highly reusable TLM-2.0 based peripheral modeling
Mixed SystemC / HDL co-simulation with Synopsys VCS and other third party HDL simulation environments enabling reuse of RTL memory controllers and other IP components
Plus, models used in Platform Architect for architecture analysis can be reused as appropriate to accelerate the creation of virtual platforms with Synopsys Virtual Prototypes for software development and software-driven verification