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Product Introduction
STING is a bare metal functional verification tool designed to serve as a platform for the design verification of RISC-V-based CPU and SoC implementations. It applies industry best practices and methodologies while providing solutions for the unique challenges of specific processor ecosystems.
The STING software stack consists of test generators, checkers, device drivers, and a lightweight kernel which can be configured into a portable program for the needs of the verification environment. The program can seamlessly boot on simulation, FPGA prototypes, emulation, or silicon and execute the constrained random, directed, or coverage-based tests that the user has specified. The highly portable stimulus is controlled by a rich file-based user input specification scheme. High levels of control are provided for every test parameter, so that every condition can be mapped to a particular test configuration.
Adopted and deployed by multiple RISC-V CPU and system vendors, STING has been used to successfully verify hundreds of system designs of varying complexity.
Key Benefits
Additional Benefits
Shift-left the design verification process
A single source of test stimulus that can be used in simulation, emulation, FPGA prototypes, and silicon
- Test stimulus scales automatically on different hardware/software configurations
- Improved throughput for test development and debug
- Developing a single set of tests saves time and verification resources
Diverse test development mechanisms
A combination of approaches to generate interesting stimulus
- A bias-based mechanism to generate traffic for constrained- random testing
- A framework for developing directed tests using snippets of ASM-like low level programming
- C++ based test development for scenarios which require complex programming constructs
Custom extensions
Custom extensions can be added for proprietary IPs
- A test content management layer allows new extensions to be randomized along with native features,
- C++ based API makes it easy to develop standalone device drivers
Easier debug
Features to facilitate debug of failing tests:
- Consistent execution environment and reliable failure reproduction make it easy to recreate a post-silicon failure in emulation or pre-silicon
- Debug hooks and mechanisms enable rapid failure debug and resolution
- Mechanism to incrementally reduce the test content from failure point for quick triage
Features
- Stable and deterministic kernel with a tiny memory and instruction footprint ideal for simulation environments
- Extremely fast test generation and execution to cover a large amount of verification space in a small amount of time
- Run the same portable stimulus on simulation, FPGA prototype, emulation, or silicon without requiring any changes
- Extensive support for all the standard, and many unratified, RISC-V extensions
- Generates extremely tight sequences of code for faster closure on coverage
- Powerful stimulus programming framework for complex test development
- Interspersed directed and random testing for better coverage under different levels of stress
- Configuration file-based input to control kernel setup, test generation, and execution
- Special kernel and library APIs for design verification are available for test developers to write stimulus generators
- Clock, power, memory, and interrupt management support provided by the kernel to the test generators and device drivers
- Support for standard verification algorithms is available with the library of test stimulus
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