Memory Is Everywhere

Every electronic system with an on-and-off switch relies on memory. From IoT to automotive and AI, each of these applications thrives on high memory bandwidth, fast throughput, and low latency. In a landscape marked by hyper-convergence, hyper-customization, digitization, and stringent reliability requirements, developing these solutions is more challenging than ever. Synopsys is here to help you shift left for faster turnaround times with the industry’s most complete, end-to-end solutions for memory development. 

Achieve Better PPA, Faster
Fast and accurate technology pathfinding, PDK generation, and design PPA assessments
Deliver Safe and Reliable Designs
High performance safety and reliability verification across product lifecycle
Shift Left to Rapidly Customize
Faster simulation, “digitized” design implementation, and faster signoff TAT


3 Pillars of Memory Design


Meet PPA Demands in a Hyper-Convergent Era

Squeezed by power, performance, and area (PPA) demands, memory designs are moving into a hyper-convergent space, consisting of multiple technologies, protocols, and architectures in one highly complex, increasingly digitized design. To facilitate development of hyper-convergent memory, Synopsys provides fast technology pathfinding, design-technology co-optimization (DTCO), and early design PPA assessments using early process development kit generation flow and integration between TCAD and custom/digital design tools. This is augmented by ultra-fast conventional and machine learning-driven simulation, and “digitized” memory design implementation flows using digital tools spanning timing characterization, digital-on-top verification, and place and route, to enable fast and accurate PPA optimization.

Quell Reliability Issues from the Start

Exploring new device structures, variants, and process flavors provides a path to better PPA. As technology gaps widen, however, modeling doesn’t capture all the effects on silicon, especially at advanced nodes. To address potential silicon reliability issues early on, Synopsys provides higher coverage with memory-specific electrical rule checking, fast chip-level electromagnetic/IR analysis with power delivery network, functional safety solutions with ISO 26262 compliance, and multi-die system design and silicon lifecycle management tools. 

Achieve Faster Turnaround Times for Hyper-Customized Designs

With every new memory protocol comes a big step up in performance and runtime. At the same time, the unique needs of different applications are driving increased customization. To scale up swiftly and meet the requirements of new protocols and unique specifications, you need faster design-to-signoff turnaround time. Synopsys can help you shift memory design left by providing faster block or chip-level simulation turnaround times, a machine learning-driven design optimization flow, faster design closure with early parasitic analysis, higher design productivity with layout reuse, and “digitized” memory design implementation flows. You can also lower integration risks and speed time-to-market with our memory IP. 

Customer Testimonials

Samsung
Kihoon Kim, Electronic Foundry Division Engineer

"To avoid huge time for current full custom design flow, Samsung Foundry evaluated Synopsys’ Partial Layout Extraction Method using Samsung Foundry Advanced Node: 4,5, and 7 nm. Based on the evaluation results, Samsung Foundry will use the PLE method in AMS ecosystem, which could enhance the Samsung Foundry’s design infra... Samsung Foundry and Synopsys keeping tight collaboration for design infra reinforcement." 

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