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Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated, while the latest technology nodes have introduced some new ones. At Synopsys, there is a corporate-wide commitment to developing broad-based solutions that address these challenges.​

​Listen to leading Memory, IP, SoC Companies and Synopsys experts shared their perspectives on the industry’s most compelling and topical challenges across four themes: Design Technology Co-optimization (DTCO), Design Shift Left, IP, and Silicon Reliability. 



Synopsys Keynote
New Paradigm in Semiconductor Design
  • Antonio Varas, Chief Strategy Officer, Synopsys
Design Technology Co-optimization (DTCO)
Flat Field Transistor (FFT) DTCO Optimization for DRAM Applications
  • Asen Asenov, CEO of Semiwise and Professor at The University of Glasgow
Memory Design Shift Left & Digitization
Innovatory Timing Margin Simulation w/ Power SPF using PrimeSim Pro
  • Tae-Jun Lee, Technical Lead, SK hynix
Memory Design Shift Left & Digitization
Static Timing Analysis of Embedded Memories: a customer’s perspective
  • John Barth, Sr. Member, Technical Staff, Synopsys
IP Solutions's MLSoC™ with LPDDR4
  • Srivi Dhruvanarayan, VP of Hardware Engineering,
Silicon Reliability
Statistically Aware and Aging-Resilient Design of SRAM
  • Kedar Janardan Dhori, Principal Engineer, STMicroelectronics
Silicon Reliability
Silicon Lifecycle Management for Emerging Memories
  • Yervant Zorian, Synopsys Fellow
Industry Panel
Need for New Paradigms in Memory Design and Development
  • Huijuan Wang, Sr. Director Physical Design, Western Digital
  • Il Park, VP of Advancement Solutions, SK hynix
  • Sandeep Bhatia, DFx Lead, Google
  • Victor Moroz, Synopsys Fellow