Energy-Efficient SoCs

Synopsys offers software-driven, low-power exploration, analysis, and optimization from architecture to signoff. At the early stages of design, Synopsys' virtual prototyping solutions enable system architects to explore and tune the macro-architecture and embedded software for low power. Software workloads can then be profiled in the power emulator to identify key windows of interest for downstream power analysis and optimization. A comprehensive solution for RTL power exploration and analysis can be used to further tune the micro-architecture for low power. Automatic power optimization techniques in the RTL-to-GDSII implementation flow ensure that the design meets power-performance-area (PPA) targets, followed by high-accuracy power signoff. The entire flow supports UPF (IEEE 1801) low-power intent.

Synopsys offers a comprehensive low-power verification solution based on UPF (IEEE 1801) power intent. This includes verification of the UPF low-power intent and exhaustive functional verification of the design in the presence of low-power techniques expressed in UPF. The solution spans static verification for low-power checks, UPF-aware formal verification, low-power simulation, early SoC architecture analysis, and optimization for power, emulation, and prototyping. Integrated with the verification solution is a unified low-power debug, planning, and coverage solution to ensure that designers can effectively root-cause low-power bugs and ensure the design meets its functional coverage goals.

Synopsys IP for Low Power SoCs enables designers to build highly functional, energy-efficient chips by offering a wide range of Interface, Foundation, and Processor IP. These solutions support advanced power-saving techniques and configurable features, helping to optimize performance while minimizing power consumption for embedded systems and SoC applications.