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Synopsys IP for Low Power SoCs
Overview
Designers are often faced with the challenge of creating complex SoCs with increased amounts of functionality while lowering power consumption. Synopsys Interface, Foundation and Processor IP portfolio supports a wide range of low power features and implements the latest advanced low power techniques.
The Synopsys Interface IP portfolio supports a wide range of protocols such as USB, PCI Express®, DDR, LPDDR, MIPI, Ethernet, Die-to-Die, Mobile Storage, DP and HDMI for SoCs requiring maximum power efficiency. Specific IP implements key power management features including multiple power rails, hibernation, power-down retention, USB battery charging, PCI Express L0 power state and L1 sub-states, MIPI PHY low power modes along with power gating techniques including the utilization of power switches, power islands or retention cells.
Foundation IP
The Synopsys Foundation IP portfolio includes memory compilers, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs to deliver the maximum performance with the lowest possible power consumption. The HPC Design Kit contains high-speed and high-density memory instances and logic cells that enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three.