The DesignWare Interface IP portfolio supports a wide range of protocols such as USB, PCI Express®, DDR, LPDDR, MIPI, Ethernet, Die-to-Die, Mobile Storage, DP and HDMI for SoCs requiring maximum power efficiency. Specific IP implements key power management features including multiple power rails, hibernation, power-down retention, USB battery charging, PCI Express L0 power state and L1 sub-states, MIPI PHY low power modes along with power gating techniques including the utilization of power switches, power islands or retention cells.
The DesignWare Fundation IP portfolio includes memory compilers, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs to deliver the maximum performance with the lowest possible power consumption. The HPC Design Kit contains high-speed and high-density memory instances and logic cells that enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three.
DesignWare ARC 32-/64-bit processors are optimized to deliver the best performance/power/area (PPA) efficiency for embedded SoCs. The ultra-compact ARC EM processors feature excellent code density, small size and very low power consumption, making them ideal for power-critical and area-sensitive embedded and deeply embedded applications. All ARC processors, including higher performance ARC HS and ARC VPX families, have an extensible instruction set that gives designers the ability to define their own custom instructions to dramatically improve application-specific performance, while reducing power consumption and memory requirements. In addition, the ARC processors are highly configurable, enabling designers to tailor them to meet the PPA requirements of each target application. Synopsys also offers the ARC EV Family of processors, which is specifically optimized to meet the demanding power and performance requirements of embedded vision applications.