Synopsys' Physical Implementation solutions offer leading quality-of-results (QoR) and improve turn-around-times (TAT), helping designers achieve the optimum Power, Performance, and Area (PPA) on SoCs. Synopsys Fusion Compiler™ is the first RTL-to-GDSII solution enabling a highly-convergent, full-flow digital implementation. Synopsys Fusion Compiler is built on a single, highly-scalable data-model with common engines for timing, extraction, synthesis, placement, legalization, clock-topology-creation and routing. These best-in-class engines form a single, unified optimization framework that is the key enabler of Synopsys Fusion Compiler’s full-flow convergence, leading quality-of-results (QoR) and enhanced time-to-results. By fusing innovative, high-capacity synthesis with Synopsys IC Compiler™ II’s industry-leading place-and-route technology onto a single data-model, Synopsys Fusion Compiler offers new levels in predictable QoR to address the challenges inherent across the industry’s most advanced designs.
Synopsys IC Compiler II provides an industry-leading, production-proven solution for Physical implementation in the Synopsys Digital Design Family. Built to support designs across all process nodes, Synopsys IC Compiler II delivers industry-best quality-of-results while enabling unprecedented productivity. Synopsys IC Compiler II is specifically designed to address aggressive performance, power area and time to market pressures with innovative solutions for flat and hierarchical design planning, early design exploration, placement and optimization, clock tree synthesis, routing, manufacturing compliance, and signoff closure. Synopsys IC Compiler II is a complete netlist to GDSII system that includes early design exploration and prototyping, design planning, block implementation, and final chip assembly for handling advanced node designs.