Synopsys ARC VPX DSP Processors

ARC VPX DSPs - Scalable Vector Processing for High-Performance Embedded Applications

Learn how Synopsys ARC VPX DSPs’ versatile yet configurable architecture addresses a range of workloads, from automotive to vision and natural language processing, and any kind of sensor fusion.

Next-Generation DSP Architecture for a Data-Centric World

The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and LiDAR processing, engine control, voice/speech recognition, natural language processing and other edge AI applications. The VPX processors are based on an enhanced ARCv2DSP instruction set and operate on 128-bit (VPX2, VPX2FS) and 256-bit (VPX3, VPX3FS) vector words, complementing the existing 512-bit VPX5 and VPX5FS based on the same very long instruction word (VLIW)/single instruction-multiple data (SIMD) architecture.

The safety-enhanced ARC VPXxFS processors integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 functional safety compliance.

The VPX processors are supported by the Synopsys ARC MetaWare Development tools, including a vector length-agnostic software programming model specifically optimized for the VPX hardware architecture. The MetaWare compiler’s auto-vectorization feature transforms sequential code into vector operations for maximum throughput.

ARC Development Tools and Software

Products and Licensable Options

ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.

  • Harvard architecture for higher performance through simultaneous instruction and data memory access
  • High-speed pipeline designed for maximum power efficiency
  • 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density

ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.

  • Add or omit hardware features to optimize the core for your target application - no wasted gates
  • The ARChitect wizard enables drag-and-drop configuration of the core

ARC Processors EXtension (APEX) technology enables users to customize their processor implementation. 

  • Add user-defined instructions to accelerate software execution and reduce code size, reducing energy consumption and memory requirements
  • Tightly couple memories and peripherals to the processors to eliminate the need for additional bus infrastructure, reducing area and latency and increasing system-level performance