DesignWare ARC VPX DSP Processors

Achieve Faster, More Accurate Data Throughput with Advanced Floating-Point DSPs

Watch the webinar to learn how!

Next-Generation DSP Architecture for a Data-Centric World

The DesignWare® ARC® VPX DSP Processors are optimized for a broad range of high-performance signal processing applications such as RADAR/LiDAR sensor node, sensor fusion, and baseband communications processing. The ARC VPX DSP processors utilize a very long instruction word (VLIW)/single instruction-multiple data (SIMD) architecture with optimized execution units for floating point and linear algebra/math computation.

The ARC VPX DSP processors are supported by the ARC MetaWare Development Toolkit, which provides a comprehensive software programming environment including optimizing vector compiler, debugger, instruction set simulator, and libraries with DSP and math functions.


ARC Development Tools and Software:

Products and Licensable Options


Supported ARC VPX Processors

Floating Point Unit (FPU)


Real-Time Trace


ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.

  • Harvard architecture for higher performance through simultaneous instruction and data memory access
  • High-speed pipeline designed for maximum power efficiency
  • 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density

ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.

  • Add or omit hardware features to optimize the core for your target application - no wasted gates
  • The ARChitect wizard enables drag-and-drop configuration of the core

ARC Processors EXtension (APEX) technology enables users to customize their processor implementation. 

  • Add user-defined instructions to accelerate software execution and reduce code size, reducing energy consumption and memory requirements
  • Tightly couple memories and peripherals to the processors to eliminate the need for additional bus infrastructure, reducing area and latency and increasing system-level performance