RTL Design and Synthesis

Next Generation RTL Design for Advanced Nodes

RTL Synthesis

RTL Architect is the latest addition to the digital design family of products. It is a predictive RTL design closure solution that provides early predictions of the impact RTL changes will have on implementability, power, performance, area and other quality metrics.

The Design Compiler family of products maximizes productivity with its complete solution for RTL synthesis and test. In the Design Compiler family of RTL synthesis products, Design Compiler NXT extends the market-leading synthesis position of Design Compiler Graphical. Design Compiler NXT incorporates the latest synthesis innovations, delivering significantly faster runtimes, improved QoR, and extremely tight RC and timing correlation with IC Compiler II. Design Compiler NXT uses advanced optimizations and shared technology with IC Compiler II place-and-route to deliver best-in-class quality-of-results at process nodes down to 5nm and beyond.

The Design Compiler family is also tightly linked to the Synopsys TestMAX family of test products for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler, for low-power synthesis and optimization; Formality for equivalence checking; and the DesignWare Library with its unequalled variety of synthesizable IP.

An important part of the design solution, Fusion Compiler is the first RTL-to-GDSII solution enabling a highly-convergent, full-flow digital implementation. Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for timing, extraction, synthesis, placement, legalization, clock-topology-creation and routing. These best-in-class engines form a single, unified optimization framework that is the key enabler of Fusion Compiler’s full-flow convergence, leading QoR and enhanced time-to-results.