Accelerate Design Innovation and Maximize Productivity
Synopsys' Design Compiler family of products maximizes productivity with its complete solution for RTL synthesis and test. Design Compiler Graphical uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best-in-class quality-of-results at all process nodes. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation.
The Design Compiler family also includes the award-winning synthesis-based test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler, for low-power synthesis and optimization; Formality for equivalence checking; and the DesignWare Library with its unequalled variety of synthesizable IP.