RTL Design and Synthesis

The Synopsys next-generation RTL design and synthesis solutions, including Synopsys RTL Architect™ and Synopsys Design Compiler® NXT, are helping engineers achieve optimal PPA at all process nodes, but especially for 5nm and below.   Synopsys RTL Architect is a predictive RTL design solution that provides early predictions of the impact RTL changes will have on implementability, power, performance, area and other quality metrics. Synopsys Design Compiler NXT, the latest evolution of the Synopsys Design Compiler family of RTL Synthesis products, incorporates state-of-the-art synthesis innovations, delivering significantly faster runtimes, improved QoR, and extremely tight RC and timing correlation with Synopsys IC Compiler™ II.

The Design Compiler family includes Synopsys Power Compiler, for low-power synthesis and optimization, and the Synopsys IP Library with its unequaled variety of synthesizable IP. It is also tightly linked to the Synopsys TestMAX family of test products for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon and Synopsys Formality for equivalence checking. 

As an important part of the Synopsys Digital Design Family, Synopsys Fusion Compiler™ is the industry's first RTL-to-GDSII solution enabling a highly-convergent, full digital implementation flow. Synopsys Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for synthesis, placement, legalization, clock-topology-creation routing, timing, and extraction. These best-in-class engines form a single, unified optimization framework that is the key enabler of Synopsys Fusion Compiler’s full-flow convergence, leading QoR and enhanced time-to-results.

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