RC and timing correlation with IC Compiler II. Design Compiler NXT uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best-in-class quality-of-results at process nodes down to 5nm and beyond. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation.
The Design Compiler family also includes the Synopsys Synthesis-Based Test Solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler, for low-power synthesis and optimization; Formality for equivalence checking; and the DesignWare Library with its unequalled variety of synthesizable IP.
A new addition to the Silicon Design family of products is Fusion Compiler. Fusion Compiler is the first RTL-to-GDSII solution enabling a highly-convergent, full-flow digital implementation. Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for timing, extraction, synthesis, placement, legalization, clock-topology-creation and routing. These best-in-class engines form a single, unified optimization framework that is the key enabler of Fusion Compiler’s full-flow convergence, leading QoR and enhanced time-to-results.