Synopsys memory VIP leverages the same proven, 100% native SystemVerilog UVM architecture as Synopsys interface and bus VIP. It offers the same advantages for ease of use, ease of integration and performance and includes verification plans, built-in coverage and support of the Verdi Protocol Analyzer protocol-aware memory debug environment. Synopsys memory VIP is a complete verification IP solution that accelerates verification closure for designers of memory controllers and SoCs.
Synopsys memory VIP can be configured on-the-fly by part number or attribute to rapidly verify interfaces against a range of components without the need to recompile. The DDR memory VIP also includes built-in support for DIMM, RDIMM and LRDIMM configurations: A single instantiation of the memory can be configured on-the-fly as any DIMM, removing the need to instantiate multiple components and implement buffering.