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Automotive Executive Guide: Rethinking Automotive Development

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SNUG

Architecture and Key Features

Specifications: JESD209-6, JESD209-5D/5C/5B/5A, JESD326-4,JESD209-3/2

Interfaces: JEDEC

Key VIP Features:

  • Single/Dual channel LPDDR 6-PIM/6/5/4/3/2, DFI MC/PHY/Monitor component   
  • Specification linked functional coverages and verification plan
  • Noise and Jitter modelling on the DQS/DQ bus
  • Passive Mode Support, Analysis Port, Bypass/Skip Initialization
  • Static/dynamic timing and configuration settings
  • Callback Hooks for CMD and Data completion, Backdoor Access (Register and Data), Error Injection  
  • Performance statistics

Debug and Analysis:

  • Verdi protocol and performance analysis
  • Protocol and timing checks
  • Trace File: Command and Data
  • Debug Ports: Commands, Bank/Row/Column addresses, MR address/opcode, Main/Bank FSM state, CMD ID, Data ID, RL, WL, WCK Sync State
  • Detailed Error Message: Ref specs section, Expected Vs Observed 
Verification IP for LPDDR

Key Protocol Features

LPDDR6-PIM/LPDDR6
LPDDR5
LPDDR4/3/2
LPDDR6-PIM/LPDDR6 + -

LPDDR6-PIM

  • Only Commands Sampling Support (WRITING_R, READING_R, PIMX_STORE,  PIMX_LOAD, ACTIVE_MB_1) and PIMX command sub-type (LOAD_MAC, LOAD_SCA, LOAD_VEC, LOAD_ACC, PIMX_RAP, PIMX_CLA, PIMX_RST, STORE_ACC).

LPDDR6

  • Efficiency mode (Static and Dynamic), Normal mode, Mixed mode
  • Configuration (4BG/4Bank), All Data Rates (1067-14400Mbps), Multi-rank including checks, Memory Densities (2Gb to 32Gb per subchannel)
  • All Commands (Write, Read, WFF, RFF, RDC, MPC, Dual Refresh, other commands)
  • Clocking (Differential CK/WCK/RDQS, WCK:CK – 2:1)
  • WCK2CK Synchronization (WCKSync, Sync off, WCKAlways ON mode) and CK Synchronization
  • All Mode Registers (MR0 to MR127 with FSP[0-2] physical register sets)
  • Trainings: WCK2CK Levelling Mode, MR12/14 CA/DQVREF, WCKDQ, Command Bus, CS, ZQ Calibration, Enhanced RDS, RDQS Toggle, RX Offset
  • System Meta Function Mode (Meta Data, Partial Array Meta Mode) 
  • Other Features: DBI, PRAC, ECC/EDC, ECS, RDQS Pre Shift, RQDS Half Rate Toggle, DVFSC, Duty Cycle Monitor (DCM) and Duty Cycle Adjuster (DCA), Vref/VRCG, WCKDQI/WCK DQO Oscillator Mode, DFE, CA Parity Check Mode, PreEmphasis, Temperature Derating AC Timing, Alert, PPR, sPPR
LPDDR5 + -

LPDDR5

  • Configurations (8/16 Bank and Bank Group Modes, All Data Rates (533-6400 Mbps), Memory Densities (2Gb to 32Gb),Normal (x16), Byte (x8) & Mixed Modes)
  • All Commands (MRW/MRR, RD/WR, ACTIVE, MPC, PDE/PDX, SRE/SRX/DSM, other commands) and Mode registers (WL/RL, Preamble/Postamble, RDQS mode, other fields)
  • WCK2CK Synchronization (4:1/2:1 ratios)
  • Multi-rank support with checks and Refresh management: RFM and DRFM
  • Duty Cycle Monitor and Adjuster , ZQ calibration and DVFS (DVFSC, DVFSQ), ECC, Write-X, DSM, data copy
  • Temperature derating and all core timings
  • Advanced features: DVFSC, DCA/RDCA/DCM, CA/CK/CS ODT, DFE, per-pin DFE, NT-ODT Data Bus Inversion and masking
  • LPDDR5 /LPDDR5X Trainings (CBT Mode 1 & Mode 2, Write Leveling, WCK-DQ Training, Read-Write based WCK-RDQS_t Training, RDQS Toggle Mode, Enhanced RDQS Toggle Mode, WCK-RDQS_t/Parity Training)
  • LPDDR5X
  • New data rates (9600,8533,7500 Mbps) and latencies (RL/WL/nWR)
  • ARFM,RDCA,E-DVFSC,CA/CK/CS ODT, Per-pin DFE, NT-ODT
LPDDR4/3/2 + -

LPDDR4

  • Data rates: 533–4267 Mbps; densities: 1Gb–32Gb
  • Supports Write Leveling, DQ Read Training, ZQ Calibration, CA, RD/WR FIFO
  • All commands, mode registers, core timings
  • FSP, DBI, configurable refresh rate, DVFS

LPDDR3

  • Data rates: 1333–2133 Mbps; 64Mb to 8 Gb densities and x8, x16, x32 wide SRAM devices
  • Supports Write Leveling, ZQ Calibration
  • All commands (MRW/MRR, RD/WR, ACTIVE, etc.), mode registers, core timings
  • Power-off, self-refresh, deep power-down, partial array self-refresh

LPDDR2

  • Data rates: 200–1066 Mbps; densities: 64Mb–32Gb
  • 64Mb to 8 Gb densities and x8, x16, x32 wide SRAM devices
  • Supports ZQ Calibration, deep power-down
  • All commands, mode registers, core timings
  • Power-off, self-refresh, deep power-down, partial array self-refresh

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