Verification IP for DFI

Specifications

• DFI 5.2/5.1, DDR5/4/3, LPDDR6/5x/5/4, DDR DIMMs(MRDIMM/RDIMM), HBM4/3/2/2e, GDDR6

DUT Types/Topology: Memory Controller and PHY

Key VIP Features

• Bypass initialization
• Active components: Controller, PHY, Passive Monitor
• Built-in verification plan with coverage and protocol checks

Debug and Analysis

• Verdi based protocol and performance analysis
• Protocol and timing checks
• Integrated coverage, verification plan, and analysis ports
• Debug ports and trace files

Key Protocol Features

• DFI Passive Monitor
  • Command/Control, Write/Read Data, Update, Status
  • PHY Master, Geardown/2N, MC-to-PHY messaging
  • Low Power, WCK control Interfaces
  • Supported Frequency Ratios: 1:1, 1:2, 1:4, 1:8
  • DFI programmable parameters
• DFI Memory Controller
  • Built-in reference tests for reset, initialization, command, and sideband traffic
  • Flexible phase specification for command driving
  • Configurable timing parameters
  • Protocol support: DDR5-MRDIMM/5/4/3, LPDDR6/5x/4, HBM4/3/2e/2, GDDR6
• DFI PHY
  • Models JEDEC initialization and PHY-initiated training
  • Power management and in-order command scheduling
  • tctrl_delay modeling
  • Protocol support: LPDDR5x, DDR-MRDIMM/5/4, HBM4/3