VC Verification IP for DFI

Synopsys® VC Verification IP for DFI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DFI based designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

Verification IP for DFI

Protocol Features

  • DFI 4.0 spec
  • All Interface groups Control
  • Write data
  • Read data
  • Update
  • Status
  • Training
  • Error
  • Low power control
  • All frequency ratios: 1:1, 1:2, 1:4
  • DDR4/LPDDR4 supported with UDIMM/RDIMM/LRDIMM

VIP Highlights

  • SystemVerilog testbench
  • Native UVM support
  • Runs natively on all major simulators and Verification Compiler™
  • Built-in verification plan and coverage
  • Built-in protocol checks
  • Protocol-aware debug
  • HTML based documentation
  • Source code visibility