VC Verification IP for LPDDR5

Synopsys® VC Verification IP for JEDEC LPDDR5 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of LPDDR5/4/3/2 based designs. VC VIP LPDDR5 is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affect performance and ease-of-use. The VIP can be integrated, configured, and customized with minimal effort, enabling designers to easily expand usage and meet organizations requirements. VIP is natively integrated with Verdi® Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

Verification IP for LPDDR5


  • Native SystemVerilog/UVM
  • Memory model certification
  • Access to vendor specification and memory models
  • Runs natively on major simulators
  • Runtime JEDEC and vendor part selection 
  • Verification Plan and Coverage
  • Built-in protocol and timing checks
  • Verdi Protocol and Memory Analyzer
  • Dynamic reconfiguration support 
  • Backdoor memory and mode registers access
  • Trace file and debug ports for easy debug
  • Bypass/fast initialization
  • Error injection & exceptions
  • Delay modeling: Fly by Delay, Trace Delays
  • DFI monitor
  • Multi Rank checks and coverage
  • AC Timings coverage

Key Features

  • LPDDR5 Specification JESD209-5
  • 8 bank, 16 bank and bank group addressing modes
  • All data rates (533 Mbps –6400 Mbps)
  • Memory densities (2GB to 32Gb)
  • All commands
  • All mode registers
  • All LPDDR5 trainings (CBT Mode 1 & Mode 2, Write Leveling, WCK-DQ Training, Read-Write based WCK-RDQS_t Training, RDQS Toggle Mode, Enhanced RDQS Toggle Mode, WCK-RDQS_t/Parity Training)
  • Configurable refresh rates
  • Write-X, DSM, ECC and data copy
  • WCK2CK synchronization
  • Temperature derating support
  • All the core timings
  • ZQ Calibrations (Background as well as Command Based)
  • Data Bus Inversion and Masking
  • Singled ended CK/WCK/RDQS support
  • Frequency Set Point (FSP 0, 1, 2)
  • Enhanced WCK-Always ON Mode support
  • Multi-Rank support
  • Normal (x16) Mode and Byte (x8) Mode support
  • Mixed Mode support
  • Refresh Management (RFM) support
  • Duty Cycle Monitor (DCM)/ Duty Cycle Adjuster (DCA) support
  • ZQ Calibration (Background as well as Command Based)
  • Post Package Repair (PPR)
  • Partial Array Self-Refresh (PASR), Partial Array Refresh Control (PARC)
  • ODT/NT-ODT & related timings support
  • Dynamic Voltage and Frequency Scaling Core (DVFSC), Dynamic Voltage and Frequency Scaling VDDQ (DVFSQ)
  • Decision Feedback Equalization (DFE)