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Call for Content Info
The Call for Content is Now Open. The Call for Content submission portal will be opening mid September. The SNUG Technical Committee will review the submitted proposals & notify presenters of preliminary program acceptance on October 17, 2024.
For more than three decades, SNUG has connected users and technical experts to network and share best practices for tackling design and verification challenges. As a SNUG presenter, you will increase your visibility among peers in the Synopsys user community. In addition to the professional recognition, you will be eligible for awards. (Please review your company’s gift acceptance policy to determine whether you may accept).
Topics
We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation:
AI, MACHINE LEARNING, BIG DATA
Exploring Synopsys AI Solutions: Targeted approaches for AI chip design integrating AI to enhance efficiency in the EDA Flow.
AUTOMOTIVE
Optimizing Automotive Innovation with Synopsys: Leveraging design, verification, Prototyping, Digital Twins, IP and software security solutions for smarter, safer cars.
ANALOG/MIXED-SIGNAL DESIGN AND SIMULATION
Enhancing Analog/Mixed-Signal Design and Simulation: Explore strategies for improving the robustness and efficiency of analog, custom, and mixed-signal designs using advanced verification, variability analysis, and integrated power/signal integrity tools. Share insights on RF analysis, minimizing design margins, accelerating design closure, and optimizing layout productivity with Synopsys tools.
DESIGN AND VERIFICATION IN THE CLOUD
Enhancing Chip Development with Synopsys Cloud: Explore how Synopsys's cloud-native tools and automation optimize design and verification processes, balancing performance and cost while ensuring security. Share insights on migrating workflows to the cloud, focusing on resource optimization, simulation, timing analysis, and elastic CPU usage in physical verification.
DIGITAL DESIGN IMPLEMENTATION
Optimizing Digital Design Implementation for Advanced Nodes: Drive innovation in advanced node designs by enhancing design flow, accelerating timing signoff, and achieving PPA targets. Collaborate with experts to refine convergence strategies, integrate early power analysis, and leverage physically aware ECO capabilities for superior outcomes.
ELECTRICAL LAYOUT VERIFICATION
Enhancing Electrical Layout Verification for Robust Designs: Strengthen power device reliability and efficiency through comprehensive ESD verification, transient effect analysis, and advanced methodologies to ensure robust and reliable electrical layouts.
ENERGY-EFFICIENT SoCs
Enhancing Energy Efficiency in Next-Generation SoCs: Explore cutting-edge strategies to optimize energy efficiency in SoCs, focusing on AI-driven power management, comprehensive hardware/software energy evaluations, and addressing the specialized power demands of smart edge devices and crypto chips.
MULTI-DIE SYSTEMS
Driving Semiconductor Innovation with Multi-Die Systems: Explore the transformation from monolithic SoCs to multi-die designs with Synopsys' comprehensive and scalable solutions. Share insights on leveraging EDA tools and IP for early architecture exploration, rapid software development, efficient die/package co-design, robust die-to-die connectivity, and enhanced manufacturing reliability.
PHYSICAL VERIFICATION
Accelerating Physical Verification for Complex SoCs: Optimize SoC integration by utilizing multi-CPU scalability for faster verification, managing dirty designs, and implementing shift-left strategies to enhance physical verification and repair processes.
SECURITY & SAFETY
Enhancing Security and Safety in Chip Design: Explore strategies for reducing chip vulnerabilities through hardware, IP, and software approaches. Share insights on the role of SoC-based root of trust (RoT), leveraging industry standards for enhanced safety and security, and implementing functional safety in hardware and software. Discuss advanced methods for hardware security verification to ensure robust and secure designs.
SIGNOFF
Accelerating Design Closure with Advanced Signoff Solutions: Explore how Synopsys' integrated design analysis and signoff solutions, including static timing analysis, power integrity, and parasitic extraction, enable designers to achieve the full performance-power-area (PPA) potential with a faster path to design closure. Share insights on leveraging these tools for efficient signal integrity, ECO closure, and transistor-level analysis.
SILICON TEST AND LIFECYCLE MANAGEMENT
Optimizing Silicon Health with Lifecycle Monitoring and Analytics: Explore how Synopsys' integrated Silicon Lifecycle Management (SLM) solutions enhance silicon health and operational metrics throughout the device lifecycle. Share insights on leveraging in-chip observability, analytics, and automation to gather actionable data from silicon to system, enabling continuous analysis and feedback.
IP
Accelerating Silicon Success with High-Quality IP: Explore how Synopsys' extensive IP portfolio, including logic libraries, embedded memories, and analog IP, enables faster and more efficient SoC designs. Share insights on leveraging Synopsys’ architecture design expertise, robust IP development, and comprehensive support to reduce integration risks and accelerate time-to-market.
SOFTWARE DEVELOPMENT & SYSTEM DESIGN
Advancing Software Development and System Design: Explore topics such as accelerating software bring-up with emulation and prototyping, software-driven power analysis for GPUs and AI, and prototyping with real-world interfaces. Delve into large complexity prototyping, pre-silicon networking system validation, SoC performance validation using emulation, trust and hardware security verification, DFT-driven emulation, and prototyping approaches for 2.5D/3D heterogeneous integration.
VERIFICATION SOFTWARE
Accelerating Verification Software: Explore how to verify the entire SoC early with Synopsys' industry-leading simulation, debug, and signoff tools, including VCS®, Verdi®, and VC Formal™, alongside silicon-proven Verification IP and advanced virtual prototyping solutions.
Important Dates
Call for Content Opens | August 15, 2024
Call for Content Portal Opens | Mid September
Call for Content Closes | October 1, 2024
Preliminary Acceptance Notification | October 17, 2024
Presentation Outline* Due | December 3, 2024
Draft Paper Due | December 3. 2024
Draft Presentations** Due | January 7, 2025
Final Acceptance & Presentation Spots Awarded | January 21, 2025
Final Paper Due | February 18, 2025
Final Presentation Due | February 25, 2025
SNUG Silicon Valley 2025 | March 19 - 20, 2025
*For submissions that are presentation only, a presentation outline must be completed. The outline template can be found in the authors kit.
** All submissions are required to turn in draft presentations by January 7, 2025.
Contact Information
If you have any questions, please contact the SNUG team.
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