Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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Call for Content Info
The Call for Content is now closed. You can check status of your proposal in the submission portal. The SNUG Technical Committee will review the submitted proposals & notify presenters of preliminary program acceptance on October 24, 2025.
For more than three decades, SNUG Silicon Valley has connected engineers, designers, and thought leaders with technical experts to network and share best practices for tackling design and verification challenges using Synopsys technologies. The Call for Content invites you to showcase how you are developing tomorrow’s products today with Synopsys solutions.
This year, in addition to our traditional SNUG program, we are excited to welcome Ansys users to the March 2026 event, which will also feature topics aligned with Simulation World as part of our expanding content offerings and growing community. As a SNUG presenter, you will increase your visibility among peers in the Synopsys user community and, in addition to professional recognition, be eligible for awards (please review your company’s gift acceptance policy to determine eligibility).
Topics
We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation:
AI, MACHINE LEARNING, BIG DATA
Exploring Synopsys AI Solutions: Targeted approaches for AI chip design integrating AI to enhance efficiency in the EDA Flow.
AUTOMOTIVE
Optimizing Automotive Innovation with Synopsys: Leveraging design, verification, Prototyping, Digital Twins, IP and software security solutions for smarter, safer cars.
ANALOG/MIXED-SIGNAL DESIGN AND SIMULATION
Enhancing Analog/Mixed-Signal Design and Simulation: Explore strategies for improving the robustness and efficiency of analog, custom, and mixed-signal designs using advanced verification, variability analysis, and integrated power/signal integrity tools. Share insights on RF analysis, minimizing design margins, accelerating design closure, and optimizing layout productivity with Synopsys tools.
DESIGN AND VERIFICATION IN THE CLOUD
Enhancing Chip Development with Synopsys Cloud: Explore how Synopsys's cloud-native tools and automation optimize design and verification processes, balancing performance and cost while ensuring security. Share insights on migrating workflows to the cloud, focusing on resource optimization, simulation, timing analysis, and elastic CPU usage in physical verification.
DESIGNING FOR ELECTRONICS RELIABILITY AND ADVANCED MANUFACTURING
Explore the transformative impact of simulation, automation, and artificial intelligence/machine learning on structural reliability across 3D/2.5D integrated circuits, advanced packaging technologies, and printed circuit boards. Sessions will address critical structural and thermal-mechanical challenges that span semiconductor manufacturing through end-system reliability, offering practical strategies for predicting failure risks, optimizing assembly, and ensuring robust performance from fabrication to final product.
DIGITAL DESIGN IMPLEMENTATION
Optimizing Digital Design Implementation for Advanced Nodes: Drive innovation in advanced node designs by enhancing design flow, accelerating timing signoff, and achieving PPA targets. Collaborate with experts to refine convergence strategies, integrate early power analysis, and leverage physically aware ECO capabilities for superior outcomes.
ELECTRICAL LAYOUT VERIFICATION
Enhancing Electrical Layout Verification for Robust Designs: Strengthen power device reliability and efficiency through comprehensive ESD verification, transient effect analysis, and advanced methodologies to ensure robust and reliable electrical layouts.
ENERGY-EFFICIENT SoCs
Enhancing Energy Efficiency in Next-Generation SoCs: Explore cutting-edge strategies to optimize energy efficiency in SoCs, focusing on AI-driven power management, comprehensive hardware/software energy evaluations, and addressing the specialized power demands of smart edge devices and crypto chips.
FORMAL VERIFICATION
Shift-left with Formal Verification: Explore how Synopsys VC Formal’s advanced formal verification technologies help teams verify some of the most complex SoC designs, find deep corner-case design bugs, and achieve formal signoff. Hear insights on how VC Formal Apps—like datapath validation, connectivity checking, X-propagation verification, sequential equivalence checking, and more—enable faster root-cause analysis, functional safety compliance, and seamless integration into simulation-based verification flows. We’ll discuss best practices, successful deployment strategies, and measurable benefits in bug detection, debug efficiency, and integrating formal analysis with simulation-based flows for improved confidence in silicon readiness.
HARDWARE ASSISTED VERIFICATION
Advancing Hardware Assisted Verification: Explore topics such as accelerating software bring-up with emulation and prototyping, software-driven power analysis for GPUs and AI, and prototyping with real-world interfaces. Delve into large complexity prototyping, pre-silicon networking system validation, SoC performance validation using emulation, trust and hardware security verification, DFT-driven emulation, and prototyping approaches for 2.5D/3D heterogeneous integration.
HIGH-POWER ELECTRONICS
Explore how low-frequency electromagnetic design drives innovation across industries—from consumer electronics and EVs to data centers and robotics. This track covers actionable strategies for optimizing wireless charging, PCB layout, and magnetic component placement, while also diving into advanced magnetic material modeling, electric motor design, and full-system integration. Learn how to solve complex design challenges by bridging electromagnetic theory with real-world applications.
IP
Accelerating Silicon Success with High-Quality IP: Explore how Synopsys' extensive IP portfolio, including logic libraries, embedded memories,and analog, enables faster and more efficient SoC designs. Share insights on leveraging Synopsys’ architecture design expertise, robust IP development, and comprehensive support to reduce integration risks and accelerate time-to-market.
MBSE: SYSTEM MODELING, DATA MANAGEMENT, AND MATERIAL INTELLIGENCE
Learn how model-based systems engineering, connected data management, and material intelligence enable early validation, cross-domain collaboration, and informed decision-making, accelerating innovation in complex systems.
MANUFACTURING
Atom-to-Fab Manufacturing Continuum: Explore how the hyperconvergence of TCAD, atomistic simulations, advanced mask synthesis, defect-aware process control, and silicon lifecycle management drive atom-to-fab modeling frameworks and intelligent feedback loops across design and manufacturing. Share how these advancements enable predictive manufacturing, first-time-right silicon, and faster yield ramp, while addressing the complexities of emerging materials/devices/processes, advanced DUV/EUV lithography, and quantum computing.
MEMORY DESIGN AND VERIFICATION
Innovations in Memory Design and Verification: Explore advanced strategies for co-optimizing memory design and technology, including the use of simulation and modeling tools for novel device and process exploration, as well as early pathfinding with virtual process design kits. Share experiences in accelerating design closure through integrated lithography rule checking and pre-layout parasitic estimation. Discuss “shift left” methodologies such as reducing block and chip-level simulation turnaround times, enhancing power distribution network simulation with heterogeneous compute acceleration, and applying machine learning-driven high sigma Monte Carlo analysis for library characterization. Present best practices for improving productivity through co-design and multi-die approaches for 2.5D and 3D memory devices. Highlight advancements in digitization, including mixed-signal verification flows for memory data paths, robust static timing analysis with aging-aware techniques, and automated place and route for memory peripheral circuits. Address silicon reliability by sharing methods for achieving higher coverage with circuit-level electrical rule checking, rapid chip-level EM/IR analysis, and the use of analog defect simulation to enhance functional safety, test coverage, and silicon failure analysis. Discuss strategies for effective silicon lifecycle management, memory protocol verification, and coverage closure, leveraging the latest design and verification methodologies.
MULTI-DIE DESIGN
Driving Semiconductor Innovation with Multi-Die Designs: Explore the transformation from monolithic SoCs to multi-die designs with Synopsys' comprehensive and scalable solutions. Share insights on leveraging EDA tools and IP for early architecture exploration, rapid software development and validation, efficient die/package co-design, robust die-to-die connectivity, and improved manufacturing and reliability.
PHYSICAL VERIFICATION
Accelerating Physical Verification for Complex SoCs: Optimize SoC integration by utilizing multi-CPU scalability for faster verification, managing dirty designs, and implementing shift-left strategies to enhance physical verification and repair processes.
SECURITY & SAFETY
Enhancing Security and Safety in Chip Design: Explore strategies for reducing chip vulnerabilities through hardware, IP, and software approaches. Share insights on the role of SoC-based root of trust (RoT), leveraging industry standards for enhanced safety and security, and implementing functional safety in hardware and software. Discuss advanced methods for hardware security verification to ensure robust and secure designs.
SIGNAL & POWER INTEGRITY
Explore advanced techniques for signal and power integrity analysis in high-speed electronics. This track explores the future of PCB design with AI-driven workflows, modeling techniques for complex interposer and rigid-flex designs, and machine learning strategies for RF and high-speed IC layout—all aimed at accelerating design cycles and ensuring performance from silicon to system.
SIGNOFF
Accelerating Design Closure with Advanced Signoff Solutions: Explore how Synopsys' integrated design analysis and signoff solutions, including static timing analysis, power integrity, and parasitic extraction, enable designers to achieve the full performance-power-area (PPA) potential with a faster path to design closure. Share insights on leveraging these tools for efficient signal integrity, ECO closure, and transistor-level analysis.
SILICON PHOTONICS & OPTICAL SYSTEMS
Discover how optics and photonics are enabling next-generation technologies across industries. This track highlights simulation-driven approaches for optimizing optical I/O, stray light control, sensor integration, and multiphysics performance, empowering engineers to innovate at the intersection of light and electronics.
SILICON TEST AND LIFECYCLE MANAGEMENT
Optimizing Silicon Health with Lifecycle Monitoring and Analytics: Explore how Synopsys' integrated Silicon Lifecycle Management (SLM) solutions enhance silicon health and operational metrics throughout the device lifecycle. Share insights on leveraging in-chip observability, analytics, and automation to gather actionable data from silicon to system, enabling continuous analysis and feedback.
THERMAL MANAGEMENT OF ELECTRONICS
Explore advanced simulation-driven strategies for managing heat in next-generation electronics, from chip to system level. This track highlights thermal challenges in semiconductors, 3DICs, mobile and consumer devices, data centers, and automotive electronics—focusing on accurate modeling, dynamic thermal behavior, and integration with mechanical and electrical design workflows.
VERIFICATION SOFTWARE
Verifying the Entire SoC: Explore how Synopsys’ industry-leading simulation, debug, and signoff tools, alongside silicon-proven verification IP can help to verify the entire SoC earlier. Share insights and successes deploying these solutions to accelerate bug discovery, improve coverage closure, and deliver reliable designs.
Important Dates
Call for Content Opens | August 14, 2025
Call for Content Closes | Extended to October 10, 2025
Preliminary Acceptance Notification | October 24, 2025
Draft Paper Due | December 2, 2025
Draft Presentation Due* | December 16, 2025
Final Acceptance & Presentation Spots Awarded | January 23, 2026
Final Paper Due | February 3, 2026
Final Presentation Due | February 10, 2026
SNUG Silicon Valley 2026 | March 11 - 12, 2026
** All submissions are required to turn in draft presentations by December 16, 2025.
Call for Content Submission Portal Form Details
Here are the questions that will be asked:
-Title
-Submission Abstract
-What is unique about this submission - Please address these questions: How applicable is this to other Synopsys users? Is the challenge/idea you will describe unique or a common issue? What's new about this paper/presentation vs. previous SNUG papers/presentations? Vs. standard industry practices?
-Does your submission discuss custom scripts?
-If Yes, can you share them?
-If you cannot share them please explain why.
-Primary Synopsys Tools/Methodology Used
-Additional Synopsys Tools/Methodology Used
-Is there anything else you would the like review committee to know?
-Has this content been presented previously?
-If yes, where?
You will also be asked to opt in to the SNUG Consent Agreement:
I hereby authorize Synopsys to record audio, video, slides, notes, quotes and other text, company logos, product logos, graphics, images, and other materials as applicable, including any names, voices, likenesses, or biographical information therein (“Materials”). Synopsys may, with no payment obligations and no need to seek additional approvals or obtain additional licenses, include and publish the Materials, as well as excerpts, summaries and other adaptations thereof, on the World Wide Web, including, but not limited to: Synopsys’ public website, SolvNetPlus website, SNUG website, Synopsys Learning Center, and social media channels. This agreement is not intended to transfer the ownership of any intellectual property rights you or your company has in its information and/or content included in the Materials. Personally identifiable information of any individuals contained in the Materials will be handled in accordance with Synopsys’ Privacy Policy, available for review at www.synopsys.com/privacy and www.synopsys.com/privacy-EEA . SNUG will be an in-person event and all presenters must be onsite at Santa Clara Convention Center to be able to participate. You acknowledge that you (your company) are responsible for any travel costs related to your participation at SNUG and that no fees can be charged to Synopsys.
Contact Information
If you have any questions, please contact the SNUG team.
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