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Call for Content Overview
The Call for Content submission portal is not yet open. In the meantime, we encourage prospective presenters to begin developing their proposals and securing any required internal approvals so you’re ready to submit once the portal launches.
Synopsys Converge takes place March 10–11, 2027, bringing together the system and silicon design communities—and the broader ecosystem—through SNUG, Simulation World, and the Executive Forum for technical deep dives, leadership perspectives, and networking.
The Call for Content invites you to showcase how you’re developing tomorrow’s products today using Synopsys solutions. Submissions help shape content across Synopsys Converge—including SNUG and Simulation World—highlighting best practices and real-world results in IP, design, verification, and system-level analysis and simulation.
The Call for Content closes September 23, 2026. The Technical Committee will review proposals and notify presenters of preliminary acceptance on October 19, 2026. After you submit, you can track your proposal status in the submission portal.
As a Converge presenter, you’ll increase your visibility in the Synopsys user community, gain professional recognition, and be eligible for awards (please review your company’s gift acceptance policy to determine eligibility).
Topics
We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation:
AEROSPACE & DEFENSE
- Design assurance for mission-critical silicon and systems
- Security, safety, reliability, and certification workflows
- Verification and signoff for aerospace and defense programs
- Supply-chain risk reduction and long-life support
- Analytics-driven test, validation, and monitoring
- Lifecycle management from design through deployment
AGENTIC AI
- Agent-driven requirements-to-implementation workflows
- AI-assisted design space exploration and optimization
- Verification closure with autonomous agents
- Signoff analysis automation and decision support
- Multiphysics correlation and automated post-processing
- Data-driven engineering insights for faster convergence
AI INFASTRUCTURE
- Architecture and design for AI compute platforms
- Memory, interconnect, and power delivery optimization
- Advanced silicon and multi-die system implementation
- EDA and analytics workflows for workload optimization
- Production reliability and utilization improvements
- Reducing system-level bottlenecks from silicon to systems
ANALOG/MIXED-SIGNAL DESIGN AND SIMULATION
- Analog and mixed-signal architecture through signoff
- Simulation acceleration and verification closure
- Performance, power, noise, and reliability optimization
- Schematic, layout, and silicon correlation
- Automation and modern AMS design flows
- Best practices for robust AMS IP and SoCs
AUTOMOTIVE
- Software-defined vehicle development
- Simulation and digital twins for automotive systems
- AI-enabled validation and system optimization
- Powertrain strategy evaluation and tradeoff analysis
- System integration across software, electronics, and mechanical domains
- Accelerating innovation while maintaining quality and safety
CONSUMER IP
- IP development and integration best practices
- Verification closure for high-quality IP and SoCs
- PPA predictability for consumer-focused designs
- Reducing integration risk and time-to-tapeout
- Design reuse and scalable IP deployment
- Balancing performance, power, area, cost, and schedule
DIGITAL DESIGN IMPLEMENTATION
- RTL-to-GDSII implementation best practices
- Synthesis, floorplanning, placement, and routing optimization
- Clocking strategies and power optimization
- Timing closure acceleration for advanced nodes
- PPA convergence and predictability improvements
- Automation methods to reduce late-stage iterations
DIGITAL ENGINEERING
- Digital engineering infrastructure and workflows
- Physics-based simulation for product design
- Connecting simulation to the digital thread
- Open ecosystem integration across engineering tools
- Reducing development cost, time, and risk
- Improving product performance through simulation-led design
ELECTRONICS
- Electronics design exploration and simulation workflows
- System-level modeling for electronics performance
- Thermal, structural, and electromagnetic analysis
- Reliability and manufacturability considerations
HARDWARE ASSISTED VERIFICATION
- Emulation workflows for large SoC validation
- FPGA prototyping for early software development
- Hardware-assisted debug and visibility improvements
- Performance and capacity optimization
- Integration with simulation and formal verification
- Reducing validation risk as design complexity scales
MULTI-DIE DESIGN
- Chiplet architecture and system partitioning
- 2.5D and 3DIC implementation workflows
- Die-to-die interconnect planning and optimization
- Power, thermal, and signal integrity across die/package interactions
- Multi-die verification and signoff methodologies
- Reducing integration risk in advanced packaging programs
SIGNOFF
- Timing, power, SI/PI, and reliability signoff
- Physical verification for advanced nodes
- Correlation and accuracy improvements
- Turnaround-time reduction for final tapeout closure
- Automation across signoff analysis workflows
- Cross-domain convergence to reduce late-stage surprises
SILICON LIFECYCLE MANAGEMENT
- Silicon instrumentation and in-field monitoring
- Production test, bring-up, and debug acceleration
- Telemetry collection and lifecycle analytics
- Yield, reliability, and quality improvement
- Automation for continuous optimization
- Reducing downtime through actionable silicon insights
VERIFICATION SOFTWARE
- Simulation and debug productivity
- Coverage closure strategies
- Regression optimization and turnaround-time reduction
- Smarter testbench and stimulus generation
- Verification automation for complex SoCs
- Integrated verification flows to reduce respin risk
Important Dates
Call for Content Opens | August 12, 2026
Call for Content Closes | September 23, 2026
Preliminary Acceptance Notification | October 19, 2026
Draft Paper (optional) Due* | November 30, 2026
Draft Presentation Due* | November 30, 2026
Revised Draft Presentation Due | January 11, 2027
Final Paper (optional) Due | January 21, 2027
Final Acceptance & Presentation Spots Awarded | February 3, 2027
Presentation Dry Runs (virtual)| February 10-19. 2027
Final Presentation Due | February 24, 2027
SNUG Silicon Valley 2026 | March 10 - 11, 2027
Final Presentation for Proceedings Due | March 12, 2027
** All submissions are required to turn in draft presentations by November 30, 2026.
Call for Content Submission Portal Form Details
Here are the questions that will be asked:
-Title
-Submission Abstract
-What is unique about this submission - Please address these questions: How applicable is this to other Synopsys users? Is the challenge/idea you will describe unique or a common issue? What's new about this paper/presentation vs. previous papers/presentations? Vs. standard industry practices?
-Does your submission discuss custom scripts?
-If Yes, can you share them?
-If you cannot share them please explain why.
-Primary Synopsys Tools/Methodology Used
-Additional Synopsys Tools/Methodology Used
-Is there anything else you would the like review committee to know?
-Has this content been presented previously?
-If yes, where?
You will also be asked to opt in to the Converge Consent Agreement:
I hereby authorize Synopsys to record audio, video, slides, notes, quotes and other text, company logos, product logos, graphics, images, and other materials as applicable, including any names, voices, likenesses, or biographical information therein (“Materials”). Synopsys may, with no payment obligations and no need to seek additional approvals or obtain additional licenses, include and publish the Materials, as well as excerpts, summaries and other adaptations thereof, on the World Wide Web, including, but not limited to: Synopsys’ public website, SolvNetPlus website, Converge website, Synopsys Learning Center, and social media channels. This agreement is not intended to transfer the ownership of any intellectual property rights you or your company has in its information and/or content included in the Materials. Personally identifiable information of any individuals contained in the Materials will be handled in accordance with Synopsys’ Privacy Policy, available for review at www.synopsys.com/privacy and www.synopsys.com/privacy-EEA . SNUG will be an in-person event and all presenters must be onsite at Santa Clara Convention Center to be able to participate. You acknowledge that you (your company) are responsible for any travel costs related to your participation at Converge and that no fees can be charged to Synopsys.
Acceptance Criteria
1. Preliminary acceptance is based on the initial submission proposal.
2. Final acceptance into the conference program agenda will be determined after the first draft of the presentation is complete, reviewed and approved by the Technical Committee.
The Technical Committee reviews and accepts submissions based on criteria that include:
- Technical Relevance: Is the topic meaningful to other engineers?
- Technical Applicability: Is the topic general enough to be helpful to other designers?
- Technical Completeness: Is the topic explored completely? Does it provide enough detail on the approach taken to analyze and address the challenge?
- Are the problems and solutions well described? Review lessons learned along the way (what was expected/unexpected, what went well/not so well).
- Is the conclusion well substantiated? Why is your solution a good one? What can other designers take away and use in their work?
- What are some ongoing areas of development or next steps which you or a peer could pursue?
- General Readability: Is the presentation well organized? Is the presentation grammatically correct and spelled correctly?
- Effective Summary of your effort and results.
Presenting at Converge
Presentation sessions are allotted a total of 30 minutes. We suggest authors plan on reserving the last 5-10 minutes for Q&A discussion with the audience.
Your presentation should be a “discussion” rather than a “reading” of the outline. While you should cover the same key points which appear in your outline and slide presentation, attendees will be most interested in hearing you describe your techniques, approach, and supported conclusions.
The planning team will communicate specific details and presentation times after final acceptances are made.
Awards
Technical Committee Best Technical Paper Award.
The winners of this award are determined by the Technical Committee members. Any user that submits a paper AND it is accepted into the conference by the Technical Committee is eligible to win the Technical Committee Best Paper award. Winners will be notified prior to the conference.
First Place: $3,000
Second Place: $2,250
Third Place: $1,500
Best Presentation Award
The winners of this award are determined during the Synopsys Converge Silicon Valley conference. Any user presentation that is accepted and presented during the conference is eligible to win the Best Presentation award. At the conclusion of each presentation, the attendees will rate the presentation by using the mobile app. At the end of the conference, the ratings will be tallied and the winners will be announced during the Awards Ceremony at the end of Day 2.
First Place: $1,000
Second Place: $750
Third Place: $500
Contact Information
If you have any questions, please contact the planning team.
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