Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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For over three decades, SNUG conferences have connected Synopsys global users, offering a platform to meet, network, and exchange ideas about chip and system design. The SNUG Roadshow in Austin is your chance to be part of this tradition and engage with fellow users and technical experts. Don’t miss this opportunity to learn, share, and inspire innovation in our industry.
Where: Hyatt Regency Austin
When: September 4, 2025 | 8:00 a.m. - 7:00 p.m.
Who: Current Synopsys customers with active licenses
Start your experience bright and early with badge pick-up at 8:00 a.m.
Be inspired by our keynote address, then dive into cutting-edge technical sessions from 9:00 a.m. to 5:00 p.m.
Cap off the day by connecting with peers and industry leaders at our exclusive customer networking reception.
Why Attend?
This year’s event offers a valuable opportunity to explore the future of technology—from silicon to systems. Here’s what you can look forward to:
- Visionary Keynote: Gain exclusive insights from John Koeter, SVP, Synopsys as he shares his perspective on the rapidly evolving semiconductor and systems landscape.
- Cutting-Edge Technical Tracks: Learn directly from Synopsys experts and fellow users about how Synopsys technology will help drive your innovation in:
- Analog & Mixed Signal: Explore cutting-edge advancements in analog and mixed-signal design with presentations on Synopsys ASO.ai, showcasing AI-driven, layout-aware optimization solutions and innovative approaches to analog node IP migration.
- Digital Implementation: Dive into the future of digital design & implementation with insights on leveraging pervasive AI, & achieving performance-per-watt goals with the latest updates to Synopsys' end-to-end power solution.
- Hardware Assisted Verification: Delve into hardware-assisted verification techniques with presentations on presilicon performance benchmarking using ZeBu Virtualizer Hybrid and advanced debug methodologies like CPU trace and DPI-based logging.
- Multi-Die Design: Discover innovations in multi-die design with presentations on 3D heterogeneous die stacking using 3DIC Compiler and integrated multiphysics timing and power signoff for 3D multi-die systems.
- Signoff: Explore advanced signoff methodologies with presentations on optimizing timing constraints throughput and quality, accelerating standard cell characterization with hybrid extraction, and achieving best-in-class PPA for high-performance designs.
- Verification Software: Unlock advanced verification software techniques with topics on enhancing power estimation accuracy using VC Replay, scaling RTL regressions with massive cloud simulations, achieving code coverage closure with reusable frameworks, and accelerating verification through FSDB reuse with VC Replay.
- Real-World Applications: Discover practical solutions and strategies from industry leaders to accelerate your projects and achieve success.
Thank You to our 2025 Sponsors
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