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The Technology Behind 90% of FinFET Designs
Most of today's cutting-edge FinFET production silicon is built with Synopsys design tools — and the same optimization technologies carry down to 28nm and other established nodes. One unified, AI-driven platform spans digital, custom analog/mixed-signal, and FPGA flows, helping engineering teams deliver maximum power, performance, area, and yield with significantly fewer iterations.
Click any section of the diagram to explore the products that power each design family, or connect with Synopsys Design Services for project-level engineering support.
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Design Families
Three integrated families on a single, AI-driven data model — pick the one that matches your design, mix and match across flows.
Digital Design Family
Unified digital design platform delivering best-in-class PPA, signoff confidence, and 3DIC integration across the entire RTL-to-GDSII flow.
Custom Design Family
Visually-assisted layout, fast SPICE simulation, and unified verification for analog, mixed-signal, RF, and memory.
FPGA-based Design
Industry-leading FPGA synthesis, debug, and rapid prototyping that accelerates ASIC verification and edge deployment.
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FAQ
Integrated circuit design is the engineering discipline of converting a chip's specification into manufacturable silicon — spanning architecture, RTL synthesis, physical implementation, signoff, and verification, across digital, analog/mixed-signal, and FPGA flows. Synopsys covers the full discipline with an integrated, AI-driven platform used to build the majority of today's cutting-edge production silicon. Learn more in our glossary.
- Choose the Digital Design Family for RTL-to-GDSII work on SoCs, processors, and any synthesizable digital logic.
- Choose the Custom Design Family for analog, mixed-signal, RF, or memory blocks where SPICE accuracy and hand-driven layout matter.
- Choose FPGA-based Design if you're shipping FPGA-based hardware or using FPGAs to prototype an ASIC before tape-out.
Most teams use more than one, and all three share a unified data model so designs flow between them without rework.
Synopsys.ai is the AI layer running across the Synopsys design platform. The flagship engine, DSO.ai, uses reinforcement learning to autonomously explore the design space — finding power, performance, and area combinations that human teams rarely reach in the same number of iterations. Customers commonly report roughly 2× faster PPA convergence, double-digit reductions in dynamic power, and measurably smaller die area on production tape-outs.
Yes. 3DIC Compiler is a first-class part of the Digital Design Family, provides a unified exploration-to-signoff platform for analysis-driven feasibility exploration, partitioning, prototyping, and floorplanning for comprehensive full-stack designs. t's the same platform leading hyperscalers and chipmakers are using today to design multi-die chips at advanced nodes.
Both. Synopsys supports the full range, from leading-edge FinFET and gate-all-around (GAA) at the most advanced foundry nodes down to 28nm, established FinFET-class nodes, and mature analog/mixed-signal processes. The same optimization technologies that deliver leading-edge PPA also benefit designs at 28nm and below — one reason the platform is behind 90% of today's cutting-edge FinFET production silicon.