Industry’s First & Most Accurate Machine Learning-driven Design Robustness Solution

Synopsys PrimeShield™ solution provides design robustness analysis and optimization at advanced nodes and enables designers to effectively improve design robustness in face of escalating process and voltage variability. It enables designers to reduce design power and boost frequency by minimizing over-pessimism, over-margin and over-design while ensuring design safety. 

Synopsys PrimeShield can rapidly identify and drive optimization of bottlenecks at the stage, path and design level that are sensitive to variations such as supply voltage drops or manufacturing variability. The patented fast statistical methods and breakthrough machine learning technology are used to firmly establish design robustness analysis as a method to minimize failure and maximize power, performance and area (PPA).  Synopsys PrimeShield delivers 100X-10,000X faster design robustness analysis and optimization than existing solutions. It is scalable to volume production system- on-chips (SoCs) with billions of transistors, while using industry standard inputs for immediate deployment.


Key Benefits

Features

As part of the Digital Design Family, Synopsys PrimeShield delivers silicon designs that are faster, lower power, more robust and more cost-effective.

Synopsys PrimeShield's innovative fast statistical engine uniquely leverages the core engines of the industry’s gold-standard Synopsys PrimeTime® signoff and Synopsys HSPICE® simulation tools. It overcomes the turnaround time challenges that previously prohibited full statistical design variation analysis with machine learning technologies, enabling analysis and optimization for every design of any size.

Accelerated by machine learning technology, the Synopsys PrimeShield solution performs fast Monte Carlo statistical simulation on critical timing paths with HSPICE accuracy within minutes, versus days or weeks required by full statistical simulations. Its patented design variation analysis with statistical correlation modeling enables analysis and optimization on large-scale SoCs with billions of cells, an analysis previously feasible only for a few dozen cells.

 

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