Electrical Layout Verification 

Synopsys Acquires Silicon Frontline Technology

Full-Chip CDM Analysis: Is Static Simulation Enough?

Efficient Power Semiconductor Devices – A Critical Success Factor for Today’s Low Power Electronics

Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level

Verification Methodologies for Domain Crossing and Transient Latch-up Damage Prevention

Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level

Numerical Simulation of Metal Interconnects of Power Semiconductor Devices

A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures

System Aware ESD Design System Mindset For A Better Foundry

Optimizing Power IC Layouts by Simulation Tools

Low-Cycle Fatigue of Multilayer Metal Stack Employed as Fast Wafer Level Monitor for Backend Integrity

RMAP – Software for Resistance Verification of Power Netsand ESD Protection Structures

Influence of Ti-Al(Cu) Backend Layer Scheme on Repetitive-Power-Pulsing Robustness

Analyze Power Nets Early and Often with P2P

Accurate Capacitance and RC Extraction Software Tool for Pixel, Sensor, and Precision Analog Designs

Characterization & Monitoring Structures for Robustness Against Cyclic Thermo- mechanical Stress

Full Chip CDM Simulation With Package Layout Included for Connectivity and Charge Distribution