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Efficient and Reliable Layout for First Silicon Success
Synopsys acquires Silicon Frontline, the leading provider of electrical layout verification solutions, providing the best-in-class blind spot detection in the design of large-scale power semiconductor devices and ESD protection networks and providing accurate optimization and validation early in the cycle to ensure first silicon success. Silicon Frontline solutions are now PrimeESD and Power Device WorkBench.
Products
Demo Videos
Resources
Blog
Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems
Research Paper
Efficient Power Semiconductor Devices – A Critical Success Factor for Today’s Low Power Electronics
Presentation
Verification Methodologies for Domain Crossing and Transient Latch-up Damage Prevention
Presentation
Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level
Research Paper
Numerical Simulation of Metal Interconnects of Power Semiconductor Devices
Research Paper
Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level
Research Paper
Low-Cycle Fatigue of Multilayer Metal Stack Employed as Fast Wafer Level Monitor for Backend Integrity
Research Paper
Influence of Ti-Al(Cu) Backend Layer Scheme on Repetitive-Power-Pulsing Robustness
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