Efficient and Reliable Layout for First Silicon Success


Synopsys acquires Silicon Frontline, the leading provider of electrical layout verification solutions, providing the best-in-class blind spot detection in the design of large-scale power semiconductor devices and ESD protection networks and providing accurate optimization and validation early in the cycle to ensure first silicon success.


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Power Devices

Resistive 3D (R3D) provides extraction and simulation of power semiconductor devices to improve design efficiency and reliability. Resistance 3D Gate (R3D gate) offers transient analysis of gate networks. Equipped with high performance solver, Electro-THermal ANalysis (ETHAN) allows thermal floor planning and transient and Static 3D electro-thermal simulation of power device networks.

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Full-Chip ESD

Electro Static Reliability Analysis (ESRA) offers comprehensive Full chip Static and Dynamic ESD Analysis verifying the interconnects, ESD devices and core devices for the Human Body model and Charged Device model events for improved design reliability.


Layout Analysis and Debug

Pillar net analysis and visualization enables fast identification of resistance and capacitance bottlenecks impacting chip’s functionality and performance at block-level, IP-level and Full-chip and offers insights to fix bottlenecks faster.


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