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Electrical Layout Verification

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Efficient and Reliable Layout for First Silicon Success

Synopsys acquires Silicon Frontline, the leading provider of electrical layout verification solutions, providing the best-in-class blind spot detection in the design of large-scale power semiconductor devices and ESD protection networks and providing accurate optimization and validation early in the cycle to ensure first silicon success. Silicon Frontline solutions are now PrimeESD and Power Device WorkBench.

Products

Demo Videos

Gate Power Device Extraction & Analysis

This video will give a brief overview of the capabilities of our gate power device analysis solution.

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Accurate ESD Simulation with Inductance

This video will give a brief introduction of the automatic inductance handling feature of Synopsys' ESD solution.

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Full-Chip Power Net Extraction & Analysis

In this video, we will give an introduction of early and often full-chip power net extraction and analysis.

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Resources

Research Paper

Electrical Layout Verification

Efficient and Reliable Layout for First Silicon Success

Products

Demo Videos

Resources

A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures

Influence of Ti-Al(Cu) Backend Layer Scheme on Repetitive-Power-Pulsing Robustness

Analyze Power Nets Early and Often with P2P

Accurate Capacitance and RC Extraction Software Tool for Pixel, Sensor, and Precision Analog Designs

Pre-Silicon Verification of Die-to-Die IP with Novel ESD Protection

Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems

Synopsys Acquires Silicon Frontline Technology

Full-Chip CDM Analysis: Is Static Simulation Enough?

Efficient Power Semiconductor Devices – A Critical Success Factor for Today’s Low Power Electronics

Verification Methodologies for Domain Crossing and Transient Latch-up Damage Prevention

Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level

Numerical Simulation of Metal Interconnects of Power Semiconductor Devices

Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level

System Aware ESD Design System Mindset For A Better Foundry

Optimizing Power IC Layouts by Simulation Tools

Low-Cycle Fatigue of Multilayer Metal Stack Employed as Fast Wafer Level Monitor for Backend Integrity

A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures

Influence of Ti-Al(Cu) Backend Layer Scheme on Repetitive-Power-Pulsing Robustness

Analyze Power Nets Early and Often with P2P

Accurate Capacitance and RC Extraction Software Tool for Pixel, Sensor, and Precision Analog Designs

Pre-Silicon Verification of Die-to-Die IP with Novel ESD Protection

Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems

Synopsys Acquires Silicon Frontline Technology

Full-Chip CDM Analysis: Is Static Simulation Enough?

Efficient Power Semiconductor Devices – A Critical Success Factor for Today’s Low Power Electronics

Verification Methodologies for Domain Crossing and Transient Latch-up Damage Prevention

Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level

Numerical Simulation of Metal Interconnects of Power Semiconductor Devices

Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level

System Aware ESD Design System Mindset For A Better Foundry

Optimizing Power IC Layouts by Simulation Tools

Low-Cycle Fatigue of Multilayer Metal Stack Employed as Fast Wafer Level Monitor for Backend Integrity

A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures

Influence of Ti-Al(Cu) Backend Layer Scheme on Repetitive-Power-Pulsing Robustness

Analyze Power Nets Early and Often with P2P

Accurate Capacitance and RC Extraction Software Tool for Pixel, Sensor, and Precision Analog Designs

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