Formality Equivalence Checking
Best Verifiable QoR...Up to 5X Faster
Speakers: Matteo Citarelli, ViaSat and Avinash Palepu, Synopsys
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Case Study of Full Chip Flat Formality with Parameterized System Verilog Interface
Divide and Conquer Strategy to Tackle Seemingly Unsolvable 25M+ Gate Design with Hybrid Hierarchical and Flat Approach
Strategies for Formality Success
Resolving Formality Conflicts for Designs Having Incomplete/Partial Power Architecture in RTL
Formality Challenges for Low Power Based Flow for Multimillion Gate Complex SoCs
A Simple RTL IP Obfuscation Flow - Using Synopsys VCS, DC and Formality
Todd Buzan, Senior Director of R&D, discusses how Formality enables aggressive optimizations in Synthesis to achieve maximal QoR.
Phillip Baraona, Senior R&D Manager, discusses how Formality’s latest adaptive distributed verification technology delivers up to 5X faster turn-around time.