It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDPs, gates or SPICE netlist views.
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ESP
Custom Design Formal Equivalence Checking Based on Symbolic Simulation
ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries.
Key Benefits
- Fast and broad coverage quickly finds bugs yielding higher quality
- Supports new device technologies through Device Model Simulation and increases productivity
- Directly verifies the SPICE netlist, eliminating the need for gate-level abstraction
Resources
Webinars
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