Custom Design Formal Equivalence Checking Based on Symbolic Simulation

ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries. It is used to ensure that two design representations are functionally equivalent. These designs may be represented as Verilog behavioral model, RTL, Gate, Switch or SPICE or .db netlist views.

Key Benefits

  • Fast and broad coverage quickly finds bugs yielding higher quality
  • Supports new device technologies through Device Model Simulation and increases productivity
  • Directly verifies the SPICE netlist, eliminating the need for gate-level abstraction
  • Variety of netlist representations supported
  • Unique features like Power Integrity Verification, Redundancy Verification, Scan Chain Verification, Library Verification, Interactive Signal Tracing