ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries.
It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDPs, gates or SPICE netlist views.
Modeling Standards to Address Designs Down to 2nm
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3D Extraction Necessities for 5nm and Below
Honey I shrunk the semiconductor
5/3nm Parasitics - What to Expect at Future Process Nodes
Format specifications and documentation for Liberty
Designer's Digest #8: IC Validator NXT Physical Verification
Super Chips: TMC BiCS FLASH Memory