ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries.
It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDPs, gates or SPICE netlist views.
Enablement Beyond the 7nm Horizon
NEW 5/3nm Parasitics - What to Expect at Future Process Nodes
NEW TSMC Certifies Synopsys Tool Flow for 7nm EUV Process
NEW 3D Extraction Necessities for 5nm and Below
NEW Synopsys and Arm Extend Collaboration to Improve Time-to-Results
Breakthrough Fusion Technology to Transform RTL-to-GDSII Flow
Design Optimization with IC Compiler II and RedHawk Analysis Fusion
NEW ESP Bridging the Gap Video Series
Smarter Library Voltage Scaling with PrimeTime
Format specifications and documentation for Liberty