ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries.
It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDPs, gates or SPICE netlist views.
Synopsys and Samsung Foundry Enables Rollout of Samsung SAFE Cloud Design Platform
Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff Flow in the Cloud
Synopsys and TSMC Collaborate to Enable Designs of HPC, Mobile, 5G, and AI SoCs
Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
Static Timing Signoff and Model Generation for Complex Analog/Mixed-Signal Designs
Achieving Design Robustness in Signoff for Advanced Node Digital Designs
Power Management Becomes Top Issue Everywhere
New Parasitic Extraction Requirements in Custom Design for the Next Wave of SoCs
AI Hardware Demands the Highest Verifiable QoR
Honey I shrunk the semiconductor
StarRC VMF vs ICV AMF Positioning
5/3nm Parasitics - What to Expect at Future Process Nodes
Format specifications and documentation for Liberty
Designer's Digest #16: The Need for 3DIC Packaging and Multi-die Integration