ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries.
It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDPs, gates or SPICE netlist views.
NEW Custom Design Platform Delivers Extraction Fusion Technology with StarRC
Synopsys Announces Availability of TSMC-certified IC Design Environment in the Cloud
Synopsys Digital and Custom Design Platforms Certified on TSMC 5-nm EUV-based Process Technology
3D Extraction Necessities for 5nm and Below
5/3nm Parasitics - What to Expect at Future Process Nodes
Format specifications and documentation for Liberty
NEW Designer's Digest #3: Advancing Custom Design