Accurate transistor-level analysis of crosstalk- delay and noise
As designs go down to 28-nm and below, crosstalk-delay comprises the majority of the total delay. Prior solutions including traditional static timing analysis with optional 3rd party crosstalk delay and noise analysis do not provide the accuracy and productivity that is required. Concurrent timing and SI crosstalk-delay and noise analysis is a must to achieve silicon success.
Accurate static timing analysis and model generation of embedded memories
As memory content in System-on-Chip (SoC) continues to increase, more and more silicon area will consist of memories with different functionality in the forms of embedded SRAM, ROM, and multi-port register files. The complexity of designs and verification challenges with embedded memories steadily increase with shrinking geometry. A new methodology with model generation capability to improve the overall engineering turn-around time is essential to meet today’s time-to-market requirements.
Full chip timing verification
Transistor- and gate-level static timing analysis need to work together to deliver full chip timing verification. A seamless and accurate timing analysis flow from custom design to gate-level with PrimeTime achieves this. To enable higher productivity, NanoTime has the same commands as PrimeTime whenever they are applicable. Figure (1) illustrates a simplified full-chip static timing signoff flow - See more at: http://www.synopsys.com/Tools/Implementation/SignOff/Pages/NanoTime.aspx#sthash.MSSwVMUB.dpuf