Transistor-level Static Signoff Analysis
NanoTime is the key foundry certified, golden signoff solution for transistor level design. It performs transistor level static timing, signal integrity and process variation analysis for complex custom designs such as CPU datapaths, register files, embedded memories and complex analog mixed-signal intellectual property (IP) blocks. As the cost of silicon failure for designs using advanced process technology such as FinFET is very significant, signoff analysis is critical to ensure that the design is free from fatal timing and noise problems. NanoTime complements dynamic simulation and is able to exhaustively check for all internal timing and noise interactions. It creates block-level timing models that can be used with PrimeTime® for full-chip signoff. NanoTime integrates seamlessly with the Synopsys custom design environment Custom Compiler® and with StarRC® Custom Ultra+ to read layout parasitics. It can also leverage Synopsys simulators Hspice and FineSim to deliver the highest accuracy.