Static Timing Analysis Solution for Custom Designs with Embedded Memories
With process geometries reaching 28-nanometers (nm) and below, there are many nanometer effects that can impact timing. Accurate analysis of these effects is required to identify real timing issues.
Synopsys’ NanoTime tool is an advanced transistor-level static timing analysis solution that addresses the emerging challenges in signal integrity (SI) analysis associated with custom designs and embedded memories.
NanoTime offers concurrent timing and SI analysis, accuracy within plus-minus five percent of HSPICE®, and has the performance required to analyze complex transistor circuits and embedded memories overnight. Its seamless integration with Synopsys’ PrimeTime® product enables full-chip analysis of designs that includes both gate- and transistor-level blocks. NanoTime is a key component of the Synopsys custom design verification solution that includes CustomSim® and HSPICE for circuit simulation and ESP-CV for symbolic simulation.