DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
This article outlines three different ways a high-speed DDR memory interface can be trained and focuses on the advantages of firmware-based training.
How to predict SerDes link performance with accurate IBIS-AMI modelling and enable more efficient SoC integration with a placement-aware 112G SerDes PHY IP.
Scalable Multicore Processors for Embedded Applications.
How efficient production test of system-in-packages (SiPs) using die-to-die PHY IP can ensure the end-product is not defective and the production yield is kept as high as possible.
Learn about the new, complex USB4 standard, including the cables, connectors and SoC building blocks.
Choose the right memory architectures and IP for AI SoCs that require new, powerful compute capabilities.
Testing PCI Express 5.0 PHY Receiver Performance in the Absence of a Controller
Neuromorphic Computing Drives the Landscape of Emerging Memories for Artificial Intelligence SoCs
Holistic Verification and Validation of Automotive IP for Functional Safety SoCs
USB4: User Expectations Drive Design Complexity