DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
Learn all about the key features of PCIe 6.0 technology and prepare for a seamless transition using optimized IP.
Learn how an integrated digital and analog architecture in 112G SerDes PHY IP can deliver maximum performance and reach in 400G/800G hyperscale data center SoCs.
See how ARC® EM Processor IP OLM enables address translation and access permission validation with minimal power and area for data intensive applications.
Learn how to implement facial recognition in edge devices with efficient, low power processors that support the latest AI algorithms and graphs.
Learn about new DesignWare® Integrity and Data Encryption (IDE) Security IP Modules that protect data center chips that use the PCIe 5.0 or CXL 2.0 protocols.
Learn how in-chip sensors and PVT monitors play a key role in performance and reliability throughout the silicon lifecycle.
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