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DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
ARTIFICIAL INTELLIGENCE
How AI in Edge Computing Drives 5G and the IoT
AI processing is moving from the cloud to the edge – learn why this matters for 5G & the IoT, and how it is changing SoC chip designs.
Learn More
die-to-die connectivity
Choosing the Right IP for Die-to-Die Connectivity
Understand the high-speed PHY IP requirements for ultra-short-reach die-to-die connectivity in hyperscale data centers.
Learn More
ARC Zone
Faster, More Accurate Data Computation with a New Generation of DSPs
Learn about the ARC VPX5 processor’s four dimensions of parallel execution for high throughput.
Learn More
LPDDR5 IP
Key Features Designers Should Know About LPDDR5
Learn how LPDDR5 standard’s features can accelerate timing closure, enhance performance, improve margins, and cut power consumption for mobile and automotive SoCs.
Learn More
PROCESSOR IP
Maximizing Performance on ARC DSP with the MATLAB/ Simulink Plugin
Create highly optimized IoT and automotive applications with Ashling’s MATLAB/Simulink plugin for ARC MetaWare Development Toolkit.
Learn More
SECURITY IP
Techniques for Ensuring Security in Processor-based SoCs
How to detect and correct security vulnerabilities that can be introduced during SoC software/hardware development, even with a secure processor.
Learn MoreVideos
- Ashling Opella-XD and Ultra-XD for ARC Debug and Trace
- Die-To-Die Connectivity
- Hardware Security Verification Using Tortuga Logic Radix-S Software at ARC Summit 2019
- ULSee Real-Time Facial Recognition & Liveness Detection System with ARC EV62 Processors
- Automotive Trends Driving New SoC Architectures
- Industry’s First USB 3.2 Gen 2x2 Interoperability Demo--Synopsys & ASMedia
- USB Fast Charging – 100W, Programmable Power Supply, and More
- USB Authentication for More Secure Systems
Articles
- SemiEngineering: Using Automotive IP For Easier Integration of Safety Into SoCs
- SemiWiki: New ARC VPX DSP IP Provides Parallel Processing Punch
- SemiWiki: IP to SoC Flow Critical for ISO 26262
- SemiWiki: Synopsys’ New Die-to-Die PHY IP – What It Means
- All About Circuits: Synopsys’ Die-to-Die PHY IP Speeds Up Cloud Computing SoC Designs
- SemiEngineering: Die-To-Die Connectivity
- SemiEngineering: How Secure is Your Face?
- SemiWiki: Synopsys and Infineon Prepare for Expanding AI Use in Automotive Applications
- Tech Design Forum: Synopsys claims 35TOPS performance from new family of embedded vision cores
News
- Synopsys Releases Industry's First Bluetooth LE Audio Codec for Power-Sensitive Audio and Voice Applications
- Synopsys to Acquire Certain IP Assets of INVECAS
- Calterah Semiconductor's Automotive Radar SoC Enters Mass Production Using Synopsys DesignWare ARC Processor IP
- Synopsys DesignWare ARC Data Fusion IP Subsystem Incorporated by Himax in Their Artificial Intelligence WiseEye ASIC
- Synopsys Completes Acquisition of Certain IP Assets from eSilicon
- Synopsys Accelerates Cloud Computing SoC Designs with New Die-to-Die PHY IP in Advanced 7nm FinFET Process
- NSITEXE Achieves First-Pass Silicon Success for High-Performance Data Flow Processor-based SoC Test Chip Using DesignWare IP
- Astera Labs Accelerates PCI Express 5.0 System Deployment in Collaboration with Intel and Synopsys
- Synopsys Launches New ARC VPX DSP Processor IP for High-performance Signal Processing SoC Designs