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DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
Complete Die-to-Die IP Solution: Use Cases and Requirements
Learn how meeting die-to-die implementation requirements in a multi-die SoC can improve modularity and yield.
Learn MoreAutomotive Cybersecurity Starts with Chips & IP
Learn about new automotive standards-compliant hardware secure module IP for safe and secure SoCs.
Learn MoreOptimize Data Center Power & Performance Using Computational Storage
Learn how the shift from traditional storage and processing solutions can boost performance and reduce the amount of data transferred.
Learn MoreAnatomy of an Integrated Ethernet PHY IP for High Performance Computing SoCs
Learn how integrating the Ethernet MAC & PHY IP accelerates the path to design closure.
Learn MoreCMOS Image Sensor Pixel Correction with OTP NVM IP
Learn how scalable, reliable OTP NVM IP for CMOS image sensors offers high security and reliability in a small footprint.
Learn MorePushing the Envelope on IP Innovation
In this Q&A with Jumana Muwafi, Sr. VP of Engineering at Synopsys, hear her vision about the future of IP in electronic design.
Learn MoreNews
- Synopsys Expands Multi-Die Solution Leadership with Industry's Lowest Latency Die-to-Die Controller IP
- Synopsys DesignWare IP Achieves Broad Industry Adoption with Multiple First-Pass Customer Silicon Successes on TSMC's N5 Process
- Synopsys DesignWare PVT Subsystem Drives Performance, Power and Silicon Lifecycle Management on TSMC's N3 Process Technology
- Synopsys Enables First-Pass Silicon Success for Early Adopters of Next-Generation Armv9 Architecture-based SoCs
- Synopsys Completes Acquisition of MorethanIP
- Synopsys and Arm Deliver Comprehensive Solutions to Increase Performance and Accelerate Time-to-Market for High-Performance Computing, Data Center and AI SoCs
- Synopsys Extends DesignWare Security, Processor IP Solutions to Address Safety and Security Requirements of Automotive Design
Videos
- DesignWare Controller and PHY IP for PCIe 6.0
- DesignWare 112G Ethernet PHY IP Operating at 53.125Gb/s
- Design Success with Foundation IP & Fusion Compiler
- Next Gen SerDes Roadmap
- Kyocera Super Resolution Printer with ARC EV Vision IP
- Super Resolution with ARC EV Processor IP
- Shifting Auto Architectures
- DesignWare Logic Library IP for TSMC N5
- Industry’s First USB4 Silicon Success
Articles
- SemiEngineering: Best 112G SerDes IP Architecture
- SemiWiki: Die-to-Die Connections Crucial for SOCs built with Chiplets
- SemiEngineering: Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
- SemiEngineering: Meeting Automotive Functional Safety Requirements With GPIOs
- SemiWiki: PCIe 6.0 Doubles Speed with New Modulation Technique
