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DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
Successful PCI Express 6.0 Designs at 64GT/s with IP
Learn all about the key features of PCIe 6.0 technology and prepare for a seamless transition using optimized IP.
Learn MoreTightly-Coupled Analog and DSP Architecture for Best 112G SerDes IP Performance
Learn how an integrated digital and analog architecture in 112G SerDes PHY IP can deliver maximum performance and reach in 400G/800G hyperscale data center SoCs.
Learn MoreHardware Overlay Management for Data Intensive, Ultra-Low Power Edge Devices
See how ARC® EM Processor IP OLM enables address translation and access permission validation with minimal power and area for data intensive applications.
Learn MorePower Efficient Facial Detection & Recognition with ARC Processor IP
Learn how to implement facial recognition in edge devices with efficient, low power processors that support the latest AI algorithms and graphs.
Learn MoreProtecting Data over PCIe & CXL in Cloud Computing
Learn about new DesignWare® Integrity and Data Encryption (IDE) Security IP Modules that protect data center chips that use the PCIe 5.0 or CXL 2.0 protocols.
Learn MoreManaging Your Silicon Lifecycle with In-Chip Sensor and PVT Monitor IP
Learn how in-chip sensors and PVT monitors play a key role in performance and reliability throughout the silicon lifecycle.
Learn MoreNews
- Synopsys Launches Industry's First Complete IP Solution for PCI Express 6.0
- Synopsys ARC EV Processor Enables Kyocera Document Solutions to Launch AI-enabled Multifunctional Printer SoC
- Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm for High-Performance Computing SoCs
- Synopsys Delivers Industry’s First Integrity and Data Encryption Security IP Modules for PCIe 5.0 and CXL 2.0 Specifications
- Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5nm Process in AI and HPC SoCs
White Papers
- Jitter Budgeting for Clock Distribution Networks in High-Speed PHYs and SerDes
- Distributed Development of IP and SoC in Compliance with Automotive ISO 26262
- Fast Cycle Approximate Simulation Using ARC nSIM NCAM
- USB 3.2: A USB Type-C Challenge for SoC Designers
- Designing ASIPs with Confidence: A Perspective on the Verification of Application Specific Instruction Set Processors
Videos
- Meeting Cloud Data Bandwidth Requirements with HPC IP
- Data Overload in The Data Center
- Silicon-Proven Automotive-Grade DesignWare IP Portfolio
- Sensor Fusion for Autonomous Vehicles: Strategies, Methods, and Tradeoffs
- Enabling DNNs at the Extreme Edge: Co-optimize Circuits, Architectures & Algorithms
- Safe & Secure SoC Architectures for Autonomous Vehicles
- Trends for Embedded Vision & AI IP in Edge Applications
- Estimating Power Early & Accurately for Smart Vision SoCs
Articles
- SemiEngineering: Safeguarding Data Over PCIe & CXL in Data Centers
- SemiWiki: USB 3.2 Helps Deliver on Type-C Connector Performance Potential
- SemiWiki: Synopsys Delivers a Brief History of AI chips and Specialty AI IP
- SemiEngineering: AI And ML Applications Require Advanced Datapath Verification
- SemiEngineering: Meeting Fundamental Interface Requirements for Camera and Display with Integrated MIPI IP
