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DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
High Accuracy Computer Vision with ISPs and Vision Processors
See how combining an ISP’s correction technique with a vision processor’s machine learning provides higher quality results.
Learn MoreConverging Cloud Computing Infrastructures with IP
Address the demands of CI and HCI systems with IP that is optimized for processing, memory and connectivity.
Learn MoreVisualizing OpenVX to Optimize Vision Applications
Learn how Percepio’s Tracealyzer for OpenVX visualization tools enable designers using ARC EV6x processors to optimize their applications for maximum performance.
Learn MoreAccelerating 32 GT/s PCIe 5.0 Designs
Learn about the design challenges of moving to a PCIe 5.0 based interface and how proven, optimized IP can help.
Learn MoreA Solid Foundation for AI-Powered SoCs
Meet power, performance, and area targets for artificial intelligence SoCs by integrating flexible building blocks of logic and memory.
Learn MoreWhich SDRAM Standard to Use and When
Learn how to choose the DDR SDRAM or HBM memory interfaces to best meet your AI, automotive, or mobile application requirements.
Learn MoreVideos
Enabling Concurrent Wireless Connectivity with DesignWare IP
Inuitive Demonstrates NU4000 Artificial Intelligence SoC with DesignWare EV6x at CES 2019
Accelerating Development of DesignWare Mixed-Signal PHY IP with Custom Compiler
PAM-4 56G Ethernet PHY IP Performance Exceeding Specification Limits
CCIX SC18: Synopsys’ DesignWare CCIX Controller and PHY IP Solutions
StradVision Deep Learning Demo for Autonomous Driving at ARC Summit 2018
SecureRF Accelerates Cryptographic Processing with DesignWare APEX Extensions
MulticoreWare Demonstrates Object Tracking and Pose Recognition at ARC Summit 2018
Articles
- Tech Design Forum: Synopsys announces DDR5 and LPDDR5 interface IP
- Tech Design Forum: The antifuse advantage for one-time programmable non-volatile memory
- Tech Design Forum: Understanding USB 3.2 and Type-C
- Tech Design Forum: Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes
- Tech Design Forum: Flexible Embedded Vision Processing Architectures for Machine-Learning Applications
- Tech Design Forum: Why AI needs security
- EE Journal: Operation: SIM Security, Integration, and the IoC
- SemiEngineering: Next-Generation Ethernet Interconnects for 400G Hyperscale Data Centers
- SemiEngineering: Dodging The Next Generation Of Car Thieves
- SemiEngineering: The Case For Antifuse OTP NVM For Secure & Reliable SoCs
- SemiEngineering: AI Begins To Reshape Chip Design
- SemiWiki: Synopsys Offers Smooth Sailing for OTP NVM
- SemiWiki: Synopsys DDR5 LPDDR5 Memory Interface IP Targets AI, Automotive, and Mobile SoCs
- SemiWiki: Car Vandals Eschew Crowbars
- ChipEstimate: Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP