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DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud
Learn about the latest high-speed interface IP standards that help minimize the latency of your high-performance SoCs in cloud systems.
Learn MoreWhy In-Memory Computing Will Disrupt Your AI SoC Development
Learn about in-memory computing IP and techniques for AI SoC designs and how it will drive significant cost, latency, and power improvements.
Learn MoreHow to Future Proof Your DSP Processor Decision for Evolving SoC Designs
Learn how to select the right DSP Processor to meet performance requirements without breaking your power and area budgets.
Learn MoreBringing Machine Learning from the Cloud to the Embedded Edge
See how SiMa.ai is using DesignWare IP to process and analyze data closer to the smart vision applications they serve.
Learn MoreIntegrated IP for MIPI Camera and Display
Learn about the MIPI standards and how they provide a high-performance interface from an image sensor or display to the SoC.
Learn MoreHardware Aware Training for Power-Efficient Keyword Spotting
Learn how new neural network keyword spotting algorithms surpass recent state-of-the-art accuracy, size, and power results, using DesignWare Embedded Memory IP benchmarks.
Learn MoreVideos
- Synopsys and Intel Full System PCIe 5.0 Interoperability Success
- Demo: Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP
- Designing Your Own Processor - Introduction to Synopsys ASIP Designer
- AI SoC Chats: Protecting Data with Security IP
- AI SoC Chats: Scaling AI Systems with Die-to-Die Interfaces
- Product Update: Broad Portfolio of DesignWare IP for Mobile SoCs
- SemiEngineering: IP Safe Enough To Use In Cars
- SemiEngineering: 112G SerDes Reliability
- Accelerate Automotive Certification with Synopsys Functional Safety Test Solution
Articles
- SemiEngineering: The Impact of 5G on Silicon Design
- SemiWiki: Synopsys is Extending CXL Applications with New IP
- SemiEngineering: Designs Beyond the Reticle Limit
- SemiEngineering: Dealing with Sub-Threshold Variation
- Dependent Failure Analysis for Safety-Critical IP and SoCs
- How Die-to-Die Connectivity Is Advancing High-Performance Computing
News
- Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5-Nanometer Process in AI and High-Performance Computing SoCs
- Synopsys Helps Advance IBM's Vision of 1,000 Times Improvement in AI Compute Performance during the Coming Decade
- TSMC Recognizes Synopsys Collaboration with Four OIP Partner of the Year Awards for IP and EDA Solutions
- Synopsys and SiMa.ai Collaborate to Bring Machine Learning Inference at Scale to the Embedded Edge
- Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications