SerDes Design Trends in the Angstrom Era: Innovations & Challenges

The semiconductor industry is in the midst of a major transformation, driven by the relentless demand for faster performance, lower power consumption, and more compact designs. Traditional scaling laws like Moore's Law, Dennard Scaling, and Amdahl's Law, which have guided progress for decades, are now reaching their limits. To keep advancing, the industry is embracing innovative solutions. One area seeing significant change is SerDes (Serializer/Deserializer) design, which is evolving rapidly with breakthroughs in process technology, power delivery, and 3D integration.

High-bandwidth SerDes IP like PCIe 6.x and PCIe 7.0, 224G PHY are leading this charge, enabling the scalability and performance needed to power AI and HPC chips, and the massive data demands of hyperscale data centers. These are the Serdes technology underlying UALink 200 and 1.6T Ultra Ethernet scale-up and scale-out links in the next-gen DC networks.

As these trends reshape the semiconductor landscape, SerDes architectures have had to undergo significant changes to remain optimal and meet the demands of next-generation applications. The transition from FinFET to GAA transistors, the adoption of backside power delivery networks, and the shift to 3D integration have all introduced new design paradigms. These innovations not only address the limitations of traditional scaling laws but also enable SerDes to achieve higher data rates, improved power efficiency, and enhanced signal integrity. However, these advancements come with their own set of challenges, requiring careful trade-offs and co-optimization to ensure balanced performance across digital, mixed-signal, and analog components.

The transition from FinFET to Gate-All-Around (GAA) FETs marks a significant milestone in transistor design. While FinFETs provided improved control over the transistor channel by surrounding it on three sides, GAA FETs take this a step further by completely enclosing the channel with the gate.

This architecture offers several advantages:

• Improved Control: GAA FETs provide better electrostatic control over the channel, reducing short-channel effects and leakage currents.
• Higher Drive Current: The increased surface area between the gate and channel enables higher drive currents, improving performance.
• Tunable Gate Widths: Designers can optimize gate widths for specific applications, balancing power and performance.

We recently announced silicon success on TSMC’s N2 GAA processes.

In digital components of SerDes, GAA FETs deliver significant improvements for PPA metrics. Shorter gate widths can be used to minimize power consumption in low-power applications, while longer gate widths can maximize performance in high-performance systems. These benefits are critical for achieving the high data rates and low latency required by modern SerDes IP.

Despite their advantages for digital design, GAA FETs pose challenges for mixed-signal and analog components, such as the IO devices in SerDes:

• Voltage Requirements: IO devices often operate at higher voltages (e.g., 1.2V or 1.5V), requiring longer gate lengths and thicker gate dielectrics. This can lead to reliability issues and performance degradation.
• Process Complexity: The need for wet and dry etching to achieve the desired gate dimensions can result in nano-scale deformation, impacting device reliability.
• Thin-Body Effects: As the channel and gate oxide layers become thinner, thin-body effects can hinder performance, particularly in high-voltage applications.

These challenges need careful design trade-offs and process optimizations to ensure balanced performance across the entire SerDes architecture.

Traditional front-side power delivery networks (FSPDN) place both power and signal resources on the same side of the chip. This approach has limitations, particularly as transistor densities increase:

• IR Drop: The increased resistance in power delivery paths leads to voltage drops, reducing efficiency.
• Coupling Effects: The proximity of power and signal vias can cause crosstalk and interference, degrading signal integrity.
• Scalability: As transistor densities grow, the available space for power and signal routing becomes increasingly constrained.

Backside power delivery networks (BSPDN) address these challenges by decoupling power and signal networks, placing power rails on the backside of the chip.

• Reduced IR Drop: Dedicated backside power rails reduce resistance and improve power delivery efficiency.
• Increased Power Density: By freeing up space on the front side, BSPDN allows for higher power densities, supporting more transistors and higher performance.
• Improved Signal Integrity: Decoupling power and signal networks minimizes crosstalk and interference, enhancing signal quality.

These advantages are critical for high-speed SerDes IP, where power efficiency and signal integrity are paramount to achieving the desired data rates.

As the demand for higher bandwidth and lower latency grows, 3D stacking has emerged as a key solution. By stacking dies vertically rather than placing them side by side, 3D integration addresses the limitations of 2D designs.

• Reduced Interconnect Length: Shorter interconnects between stacked dies reduce latency and power consumption.
• Smaller Form Factor: Vertical stacking enables more compact designs, ideal for space-constrained applications.
• Heterogeneous Integration: Different types of dies (e.g., compute, memory, and IO) can be integrated into a single package, enhancing functionality and performance.
• Reusability: IO chiplets can be reused across multiple designs, reducing development costs.

• Thermal Dissipation: The lack of heat sinks between stacked dies limits thermal dissipation, leading to potential overheating.
• Coupling Effects: TSVs introduce coupling effects and interference, which can degrade performance.
• Reliability: Warpage, cracking, and other mechanical issues can compromise the integrity of the stacked dies.

In SerDes, 3D stacking impacts both the digital and analog components:

• Digital Components: Reduced interconnect lengths improve latency and power efficiency.
• Analog Components: Coupling effects and thermal challenges require careful design and optimization to maintain signal integrity.

Achieving these benefits requires advanced design methodologies and co-optimization to ensure that SerDes IP can meet the demands of next-generation applications.

To address the complexities of Angstrom-scale nodes, BSPDN, and 3D stacking, Design Technology Co-Optimization (DTCO) has become essential. DTCO involves the simultaneous optimization of design and process technologies to achieve the best possible PPA metrics.

1. Thermal and Power Co-Optimization:
   • Evaluate floorplans to minimize hotspots and spread TSVs for better thermal management.
   • Balance power and performance trade-offs for different use cases.
2. Early Foundry Collaboration:
   • Engage with foundries during the early stages of process development to validate IP designs.
   • Perform reliability checks, such as static and dynamic aging, to ensure long-term performance.
3. Iterative Feedback:
   • Continuously refine designs based on feedback from foundry models and early silicon results.

DTCO enables a holistic approach to SerDes design, ensuring that performance, power, and reliability targets are met while addressing the challenges of advanced process technologies.

The evolution of SerDes design is being shaped by three major trends: Angstrom-scale innovations, backside power delivery, and 3D stacking. These advancements bring significant benefits, such as improved performance, reduced power consumption, and smaller form factors. At the same time, they introduce new challenges, including process complexity, thermal management, and reliability concerns, which require innovative solutions and advanced design methodologies.

Synopsys is leading this transformation with its best-in-class, broad IP portfolio, including SerDes IP such as PCIe 6.0, PCIe 7.0, UALink, 224G Ethernet, and key HPC IP such as UCIe, HBM, and CXL, designed to accelerate time-to-market and minimize integration risk. Additionally, Synopsys provides advanced methodologies like DTCO, with tools such as the 3DIC Compiler for 2.5D and 3D heterogeneous integration, and AI-driven optimization with 3DSO.ai. As we move deeper into the Angstrom era, Synopsys proven IP and industry-leading multi-die solutions are enabling the performance required to meet the demands for the next chapter of AI and HPC designs.