What is SerDes (Serializer/Deserializer)?

Definition

SerDes is a functional block that Serializes and Deserializes digital data used in high-speed chip-to-chip communication. Modern SoCs for high-performance computing (HPC), artificial intelligence (AI), automotive, mobile, and Internet-of-Things (IoT) applications implement SerDes that can support multiple data rates and standards like PCI Express (PCIe), MIPI, Ethernet, USB, USR/XSR.  

SerDes (serializer/deserializer) Figure 1  | Synopsys

A SerDes implementation includes parallel-to-serial (serial-to-parallel) data conversion, impedance matching circuitry, and clock data recovery functionality. The primary role of SerDes is to minimize the number of I/O  interconnects.

Why do we need SerDes?

Distributed data processing in ICs need high speed data transfer between the ICs. Parallel and serial are the two options to transfer data between chips. Parallel data transfer requires multiple connections between ICs compared to serial data transfer that only needs one pair of connection. 

SerDes (serializer/deserializer) Figure 2  | Synopsys

As shown in the table above, serial data transfer can be an ideal option due to its advantages, such as low-power consumption, robust EMI performance, and easy package design.

SerDes applications

SerDes is the most fundamental building block of a physical layer for chip-to-chip interconnect systems:

 

SerDes + Physical Coding Sublayer (PCS) = PHY or Physical Layer

 

The Open Systems Interconnection (OSI) model defines physical layer, or PHY, as an abstraction layer responsible for transmission and reception of the data. It is the lowest layer in the OSI model, which also includes: 

  • Application layer
  • Presentation layer
  • Session layer
  • Transport layer
  • Network layer
  • Datalink layer

Different protocols suggest various abstraction division for a PHY. For example, 100G PHY defined by IEEE 802.3 has the following abstraction layers:

SerDes (serializer/deserializer) Figure 3  | Synopsys

In this model SerDes will implement PMA/PMD sublayers, which is the logical sub-block responsible for interface initialization, encoding decoding, and clock alignment. 

What PHY IP solutions does Synopsys offer?

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs implemented in today’s most widely adopted devices and systems across a wide range of markets including: 

Synopsys’ DesignWare High-Speed SerDes PHY IP portfolio encompasses 56G and 112G Ethernet PHYs, High-Bandwidth Interface (HBI) and 112G USR/XSR die-to-die PHYs, and multi-protocol 32G PHYs that support PCIe 5.0 and Ethernet protocols, all of which are available in the most advanced FinFET processes. Learn more at: