The DesignWare 112G Ethernet PHY IP enables true long reach channels for up to 800G hyperscale data center SoCs requiring high bandwidth and low latency. Using leading-edge design, analysis, simulation, and measurement techniques, the 112G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The PHY is small in area, high in performance, and supports chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects.
The 112G Ethernet PHY’s flexible layout maximizes bandwidth per die-edge by allowing placement of square macros in a multi-row structure and along all edges of the die. The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4), Non- Return-to-Zero (NRZ) signaling, as well as independent, per lane data rates for ultimate flexibility to address broad range of protocols and applications. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithms provide robust performance across voltage and temperature variations. The low jitter PLLs, clock, and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and non-destructive 2D eye monitor capability provide on-chip testability and visibility into channel performance.
DesignWare 112G Ethernet PHY IP Datasheet
DesignWare 112G Ethernet PHY IP in TSMC N7 ProcessSee the transmitter and receiver testing of Synopsys' DesignWare 112G Ethernet PHY IP in TSMC's N7 process. A 106.25Gb/s PAM-4 transmitter eye diagram shows good symmetry and height/width. The receiver is tested with channels of up to 40dB of loss. Performance metrics such as bit error rate (BER) and on-chip eye opening (via non-destructive 2D eye monitor) are reported.
Downloads and Documentation
- Supports full-duplex 9.9 to 112Gbps data rates
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of chip-to-chip, chip-to-module, and backplane interconnects
- Provides comprehensive 112G solution with routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis
- DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
- Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
- High-performance receive equalization supports channel loss of 35dB
- Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature
- Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance