DesignWare 112G Ethernet PHY IP

The DesignWare 112G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the 112G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The PHY is small in area, low in power consumption, and high in performance, supporting channel loss of 35dB. It meets the needs of chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects.

The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and Non- Return-to-Zero (NRZ) signaling to deliver up to 800G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the DesignWare Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.

Contact us to discuss your 112G Ethernet PHY IP needs for your next high-performance SoC design.

DesignWare 112G Ethernet PHY IP Datasheet

 

Highlights
  • Supports full-duplex 9.9 to 112Gbps data rates in 1, 2, and 4 lanes
  • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired network infrastructure
  • Supports IEEE 802.3ck and OIF standards electrical specifications
  • Meets the performance requirements of chip-to-chip, chip-to-module, and backplane interconnects
  • DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
  • Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
  • High-performance receive equalization supports channel loss of 35dB
  • Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature
  • Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance