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DesignWare Videos
Featured Processor Solutions Video: SecureRF Accelerates Cryptographic Processing with APEX Extensions
See how SecureRF uses ARC® Processor Extension (APEX) technology to add their own custom hardware to the ARC processor, boosting performance by 4X and reducing power consumption for their signature verification method.
Drake Smith, SecureRF and Rich Collins, Synopsys
Featured Embedded Vision Video: StradVision Deep Learning Demo for Autonomous Driving at ARC Summit 2018
StradVision has developed SVNet, a deep-learning-based object detection of 6 object classes, which is robust for bad lighting conditions, small objects, and up to 75% occlusion. StradVision’s SVNet can run on the DesignWare EV6x Embedded Vision Processor to reduce area and power consumption compared to GPUs.
Heo Chungbin, Optimization Engineer
Gordon Cooper, EV Product Marketing
Featured Ethernet Video: PAM-4 56G Ethernet PHY IP Performance Exceeding Specification Limits
See the latest silicon results of Synopsys’ DesignWare 56G Ethernet PHY IP in PAM-4 and NRZ modes. The video shows the IP passing electrical compliance test suites and its performance far exceeding the standard specification limits for jitter and interference tolerance. Synopsys’ 56G Ethernet PHY IP solution’s scalable architecture enables 112G interfaces for 800G Ethernet applications.
Synopsys
Featured Security Video: Truphone eSIM and DesignWare tRoot Fx Hardware Secure Module
See how designers can provision any IoT device using Truphone’s iSIM solution and DesignWare tRoot Fx HSMs. Using Truphone bootstrap connectivity, the demo shows how in-the-field remote device activation is possible for any mobile operator and can remove the logistics and costs associated with physical SIM cards.
Rich Collins, Synopsys and Michael Moorfield, Truphone
Featured PCIe Video: High-Performance NVMe Solution with Synopsys and EpoStar
This interview video shows how designers can deliver robust and reliable SSDs with Synopsys’ DesignWare Endpoint Controller IP for PCI Express and EpoStar’s NVMe controller. The solutions interoperate to deliver a flexible NVMe solution that allows high throughput at full line rates and optimized traffic for highest performance. For more information, visit www.synopsys.com/pcie.
Richard Chen, Vice President, EpoStar Electronics Corp., Gary Ruggles, Sr. Product Marketing Manager, Synopsys
Test & Repair Requirements for Autonomous Vehicles
Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.
Joachim Kunkel, General Manager of the Solutions Group, Synopsys
Featured USB Video: Synopsys Demonstrates Certified DisplayPort IP at HBR3 Rates
Eric Huang demonstrates Synopsys’ DesignWare DisplayPort IP solution passing compliance tests using two lanes of HBR3 rates at the highest resolutions. Compliance testing is a critical step in ensuring a solution’s reliability and interoperability.
Eric Huang, Sr. Product Marketing Manager, Synopsys
Featured Bluetooth Video: Accelerating SW Development & IP Evaluation with DesignWare Bluetooth IP
Easily integrate Bluetooth 5 & Bluetooth Mesh capabilities into IoT SoCs, and get a jump start on designing with industry-proven open source software. The demo features a complete solution including DesignWare Bluetooth LE PHY & Link Layer IP and ARC EM Processor.
Ron Lowman, Marketing Manager, Synopsys
IP for Machine Learning Applications
The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements.
Navraj Nandra, Sr. Director of Marketing, Synopsys
Sensor Connectivity with MIPI I3C
This video highlights the advantages of MIPI I3C for system-level sensor connectivity in mobile, automotive and IoT applications. A simple two-wire interface, I3C supports speeds up to 33 megabits per second and shares a 2-wire bus with multiple sensors. Synopsys DesignWare MIPI I3C IP supports the latest I3C specification and offers a complete solution for sensor connectivity.
Synopsys
55-nm IoT Platform
This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.
Ron Lowman, Strategic Marketing Manager, Synopsys
Under The Hood: What It Takes To Meet Automotive Compliance
This presentation provides insights into the technical specifications and design decisions for developing automotive grade IP, which helps accelerate compliance of automotive systems and ensures products meet automotive standards such as ISO 26262 functional safety, AEC-Q100 reliability testing and TS 16949 quality management.
Navraj Nandra, Sr. Director of Marketing, Synopsys
Training DIMMs to 3200 Mbps with DesignWare DDR4/3 PHY IP
See how the Synopsys DDR4/3 PHY IP can program and train a wide variety of UDIMMs, RDIMMs, LRDIMMs and 3DS-DIMMs with excellent signal integrity. You’ll also see the results from a shared AC system and when reflection is introduced to the system.
Marc Greenberg, Director of Product Marketing, Synopsys Brett Murdock, Solutions Architect, Synopsys
Featured Processor Solutions Video: Secure Your IoT Device with Ultra-Low Power ARC Processors
Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum.
Synopsys
Designing 7-nm IP, Bring It On Moore!
In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA req's. See how quantum effects impact FinFET designs in terms of fin width & height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance & power improvements.
Navraj Nandra, Sr. Director of Marketing, Synopsys
What is ASIP Designer?
See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements.
Bo Wu, Technical Marketing Manager and Steve Cox, Sr. Manager, Business Development, Synopsys
Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio
John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.
John Blyler, Editorial Director, IoT Embedded Systems Ron Lowman, Strategic Marketing Manager for IoT, Synopsys
SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching
See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth
Mat Loikkanen, SATA R&D, Synopsys