DesignWare Videos

Featured Video: DesignWare 56G Ethernet PHY IP Operating Across 400G Interconnects

This OFC 2019 video demo shows Synopsys’ 56G Ethernet PHY IP running across multiple 400G interconnects. The IP is capable of operating across backplanes and optical, copper cables in QSFP-DD, OSFP, and SFP-DD form factors, meeting the IEEE 802.3cd standard.   

Rita Horner, Sr. Technical Marketing Manager, Synopsys

Scott Emery, Hardware Engineer, Synopsys

Featured Wireless Connectivity Video: Enabling Concurrent Wireless Connectivity with DesignWare IP

This video showcases concurrent wireless connectivity across Bluetooth low energy, Thread, and Zigbee protocols using DesignWare IP. The Synopsys IP provides a low-power wireless interface solution for battery-operated, smart IoT devices with silicon-proven PHYs and controllers compliant with the latest versions of the standards. 

Ron Lowman, Marketing Manager, Synopsys

Featured Embedded Vision Video: Inuitive Demonstrates NU4000 Artificial Intelligence SoC with DesignWare EV6x at CES 2019

Inuitive demonstrated their NU4000 SoC for 3D imaging and vision at CES 2019. The NU4000 uses Synopsys’ DesignWare EV6x Embedded Vision Processor IP with CNN Engine. The EV6x can execute on-chip deep learning tasks for artificial intelligence and vision such as object detection, facial recognition, and object tracking.

 

Maximizing SoC Throughput with Synopsys DesignWare CCIX IP

This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX  PHY and controller IP.

Featured Processor Solutions Video: SecureRF Accelerates Cryptographic Processing with APEX Extensions

See how SecureRF uses ARC® Processor Extension (APEX) technology to add their own custom hardware to the ARC processor, boosting performance by 4X and reducing power consumption for their signature verification method. 

Drake Smith, SecureRF and Rich Collins, Synopsys

 

 

Featured Video: DesignWare 56G Ethernet PHY IP Operating Across 400G Interconnects

This OFC 2019 video demo shows Synopsys’ 56G Ethernet PHY IP running across multiple 400G interconnects. The IP is capable of operating across backplanes and optical, copper cables in QSFP-DD, OSFP, and SFP-DD form factors, meeting the IEEE 802.3cd standard.   

Rita Horner, Sr. Technical Marketing Manager, Synopsys

Scott Emery, Hardware Engineer, Synopsys

 

Truphone eSIM and DesignWare tRoot Fx Hardware Secure Module

See how designers can provision any IoT device using Truphone’s iSIM solution and DesignWare tRoot Fx HSMs. Using Truphone bootstrap connectivity, the demo shows how in-the-field remote device activation is possible for any mobile operator and can remove the logistics and costs associated with physical SIM cards. 

Rich Collins, Synopsys and Michael Moorfield, Truphone

 

DesignWare PHY IP for PCIe 5.0 in Silicon Operating at 32 GT/s

This video shows the Synopsys PHY IP for PCI Express (PCIe) 5.0 operating at 32 GT/s data rate across a long compliance channel. The wide open receiver eye and the bath tub plots show the PHY meeting the PCIe 5.0 specification for performance and bit error rate. Accelerate your shift to PCIe 5.0 designs with the Synopsys DesignWare Controller and PHY IP solutions.

Christiane de Verteuil, R&D Manager, Synopsys

 

 

Test & Repair Requirements for Autonomous Vehicles

Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.

Joachim Kunkel, General Manager of the Solutions Group, Synopsys

Synopsys Demonstrates Certified DisplayPort IP at HBR3 Rates

Eric Huang demonstrates Synopsys’ DesignWare DisplayPort IP solution passing compliance tests using two lanes of HBR3 rates at the highest resolutions. Compliance testing is a critical step in ensuring a solution’s reliability and interoperability. 

Eric Huang, Sr. Product Marketing Manager, Synopsys

IP for Machine Learning Applications

The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements. 

Navraj Nandra, Sr. Director of Marketing, Synopsys

Sensor Connectivity with MIPI I3C

This video highlights the advantages of MIPI I3C for system-level sensor connectivity in mobile, automotive and IoT applications. A simple two-wire interface, I3C supports speeds up to 33 megabits per second and shares a 2-wire bus with multiple sensors. Synopsys DesignWare MIPI I3C IP supports the latest I3C specification and offers a complete solution for sensor connectivity. 

Synopsys

55-nm IoT Platform

This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.

Ron Lowman, Strategic Marketing Manager, Synopsys

Under The Hood: What It Takes To Meet Automotive Compliance

This presentation provides insights into the technical specifications and design decisions for developing automotive grade IP, which helps accelerate compliance of automotive systems and ensures products meet automotive standards such as ISO 26262 functional safety, AEC-Q100 reliability testing and TS 16949 quality management.

Navraj Nandra, Sr. Director of Marketing, Synopsys

 

Training DIMMs to 3200 Mbps with DesignWare DDR4/3 PHY IP

See how the Synopsys DDR4/3 PHY IP can program and train a wide variety of UDIMMs, RDIMMs, LRDIMMs and 3DS-DIMMs with excellent signal integrity. You’ll also see the results from a shared AC system and when reflection is introduced to the system. 

Marc Greenberg, Director of Product Marketing, Synopsys Brett Murdock, Solutions Architect, Synopsys

Featured Processor Solutions Video: Secure Your IoT Device with Ultra-Low Power ARC Processors

Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum.

Synopsys

Designing 7-nm IP, Bring It On Moore!

In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA req's. See how quantum effects impact FinFET designs in terms of fin width & height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance & power improvements.

Navraj Nandra, Sr. Director of Marketing, Synopsys

What is ASIP Designer?

See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements. 

Bo Wu, Technical Marketing Manager and Steve Cox, Sr. Manager, Business Development, Synopsys

Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio

John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.

John Blyler, Editorial Director, IoT Embedded Systems Ron Lowman, Strategic Marketing Manager for IoT, Synopsys

SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching

See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth

Mat Loikkanen, SATA R&D, Synopsys