DesignWare Videos
IP Driving Automotive SoCs
If you are designing SoCs for ADAS, where safety and reliability are non-negotiable and a split second matters, then you want to know about Synopsys DesignWare IP for Automotive.
End-to-End System with DesignWare IP for PCIe 5.0 at 32GT/s
This demo shows Synopsys’ complete PHY and controller IP solutions for PCI Express (PCIe) 5.0 operating at 32GT/s. The Synopsys Root Complex controller and Endpoint controller together with the Synopsys 32G PHY IP are able to successfully link up and transfer data at the required 32GT/s data rate, achieving a throughput of 3480GB/s, which is close to the theoretical maximum achievable for a x1 link.
DesignWare PHY IP for PCIe 5.0 at 32GT/s Performance Across Multiple Channels
This video shows Synopsys’ PHY IP for PCI Express (PCIe) 5.0 performance at 32GT/s data rates across Samtec’s ExaMax backplane and Amphenol’s’ CEM 5.0 connector. The PHY shows wide open eyes across more than 36db channel loss and 1e-15 bit error rate. The demo also shows collaboration with Keysight to demonstrate accurate correlation of IBIS-AMI model to silicon results.
DesignWare PHY IP Meeting the PCIe 5.0 Rev. 1.0 Specification
This video features Synopsys’ DesignWare PHY IP for PCI Express 5.0 meeting the Rev. 1.0 specification’s channel performance and jitter tolerance. The IP operates at 32GT/s data rate and exceeds the required 36 dB channel loss to enable high-throughput over the toughest, long-reach channels. Accelerate your move to PCI Express 5.0 with Synopsys’ DesignWare IP.
Featured Wireless Connectivity Video: Enabling Concurrent Wireless Connectivity with DesignWare IP
This video showcases concurrent wireless connectivity across Bluetooth low energy, Thread, and Zigbee protocols using DesignWare IP. The Synopsys IP provides a low-power wireless interface solution for battery-operated, smart IoT devices with silicon-proven PHYs and controllers compliant with the latest versions of the standards.
Ron Lowman, Marketing Manager, Synopsys
Featured Embedded Vision Video: Accelerate Auto Design with ARC EV6x Embedded Vision Processors
Check out the DesignWare ARC EV6x Embedded Vision Processor IP running algorithms for automotive applications for object detection and classification as well as motion tracking.
Maximizing SoC Throughput with Synopsys DesignWare CCIX IP
This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX PHY and controller IP.
Featured Processor Solutions Video: Developing RADAR for ADAS Applications using DesignWare® ARC® Processors
Learn about Synopsys’ Processor Solutions that meet high-computation and specialized processing requirements, enabling design teams to create highly-efficient and differentiated SoCs for RADAR applications.
Graham Wilson, Synopsys
Featured Video: DesignWare 56G Ethernet PHY IP Operating Across 400G Interconnects
This OFC 2019 video demo shows Synopsys’ 56G Ethernet PHY IP running across multiple 400G interconnects. The IP is capable of operating across backplanes and optical, copper cables in QSFP-DD, OSFP, and SFP-DD form factors, meeting the IEEE 802.3cd standard.
Rita Horner, Sr. Technical Marketing Manager, Synopsys
Scott Emery, Hardware Engineer, Synopsys
Truphone eSIM and DesignWare tRoot Fx Hardware Secure Module
See how designers can provision any IoT device using Truphone’s iSIM solution and DesignWare tRoot Fx HSMs. Using Truphone bootstrap connectivity, the demo shows how in-the-field remote device activation is possible for any mobile operator and can remove the logistics and costs associated with physical SIM cards.
Rich Collins, Synopsys and Michael Moorfield, Truphone
Test & Repair Requirements for Autonomous Vehicles
Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.
Joachim Kunkel, General Manager of the Solutions Group, Synopsys
World’s First USB 3.2 Demonstration
Join Eric Huang and Gervais Fong as they demonstrate the world's first USB 3.2 host and device IP communicating at USB 3.2 speeds over a standard USB Type-C cable.
Amazing AI SoCs
Amazing AI starts with silicon and software, designs that innovative teams around the world create every day. But in the end, it’s not just about chips. It’s about making transportation safer, making human connections stronger, and making our daily interactions more meaningful.
IP for Machine Learning Applications
The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements.
Navraj Nandra, Sr. Director of Marketing, Synopsys
Sensor Connectivity with MIPI I3C
This video highlights the advantages of MIPI I3C for system-level sensor connectivity in mobile, automotive and IoT applications. A simple two-wire interface, I3C supports speeds up to 33 megabits per second and shares a 2-wire bus with multiple sensors. Synopsys DesignWare MIPI I3C IP supports the latest I3C specification and offers a complete solution for sensor connectivity.
Synopsys
55-nm IoT Platform
This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.
Ron Lowman, Strategic Marketing Manager, Synopsys
Under The Hood: What It Takes To Meet Automotive Compliance
This presentation provides insights into the technical specifications and design decisions for developing automotive grade IP, which helps accelerate compliance of automotive systems and ensures products meet automotive standards such as ISO 26262 functional safety, AEC-Q100 reliability testing and TS 16949 quality management.
Navraj Nandra, Sr. Director of Marketing, Synopsys
Selecting the right DDR Memory IP for Greatest Impact
SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design.
Featured Processor Solutions Video: Secure Your IoT Device with Ultra-Low Power ARC Processors
Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum.
Synopsys
Designing 7-nm IP, Bring It On Moore!
In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA req's. See how quantum effects impact FinFET designs in terms of fin width & height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance & power improvements.
Navraj Nandra, Sr. Director of Marketing, Synopsys
What is ASIP Designer?
See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements.
Bo Wu, Technical Marketing Manager and Steve Cox, Sr. Manager, Business Development, Synopsys
Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio
John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.
John Blyler, Editorial Director, IoT Embedded Systems Ron Lowman, Strategic Marketing Manager for IoT, Synopsys
SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching
See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth
Mat Loikkanen, SATA R&D, Synopsys