DesignWare IP Videos

DesignCon 2021 112G Ethernet & PCIe 6.0 IP Demos

This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.  

Complete DesignWare 400G/800G Ethernet IP

This video features Synopsys' complete DesignWare Ethernet IP solution including MAC, PCS and PHY for speeds up to 400G/800G. 

Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Processor IP

This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on ARC EV7x processor with DNN engine. It shows 3D boxes rendered onto objects detected in the video frames, enabling the development of driver assistance systems.

Design Success with Foundation IP & Fusion Compiler

When is 1+1 greater than 2? When using DesignWare Foundation IP & Fusion Compiler! Join Raymond and Yung in their discussion of a customer that benefited from the combination of Fusion Compiler’s machine learning and Foundation IP cells and macros.   

DesignWare Controller and PHY IP for PCIe 6.0

See a demo of Synopsys’ complete IP solution for PCIe 6.0 technology showing the controller operating at 64GT/s in FLIT mode and the PAM-4 PHY in 5-nm process achieving two orders of magnitude better BER with 32dB PCIe channel.

Meeting Cloud Data Bandwidth Requirements with HPC IP

As people continue to work remotely, demands on cloud data centers have never been higher. Chip designers for high-performance computing (HPC) SoCs are looking to new and innovative IP to meet their bandwidth, capacity, and security needs. 

Silicon-Proven Automotive-Grade DesignWare IP

Get the latest on Synopsys' automotive IP portfolio supporting ISO 26262 functional safety, reliability, and quality management standards, with an available architecture for SoC development and safety management.

AI SoC Chats: Protecting Data with Security IP

Understand the threat profiles and security trends for AI SoC applications, including how laws and regulations are changing to protect the private information and data of users. Learn how DesignWare Security IP and Hardware Root of Trust can help designers create a secure enclave on the SoC and update software remotely.

Broad Portfolio of IP for Mobile SoCs

Get the latest update on DesignWare IP for mobile SoCs, including MIPI C-PHY/D-PHY, USB 3.1, and UFS, which provide the necessary throughput, bandwidth, and efficiency for today’s advanced mobile SoCs.

Demo: Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP

See ARC EM9D Processors run a handwriting character recognition neural network graph to infer the letter that is written.     

Synopsys and SK hynix Discuss HBM2E at 3.6Gbps

In this video interview hear from Keith Kim, Team Leader of DRAM Technical Marketing at SK hynix, discussing the wide adoption of HBM2E at 3.6Gbps and successful collaboration with Synopsys to validate the DesignWare HBM2E IP at the maximum speed.

DesignWare MIPI C-PHY/D-PHY IP Performance at 24 Gbps

This video features the DesignWare MIPI C-PHY/D-PHY IP interoperating with an image sensor in C-PHY mode up to 3.5 Gsps per trio and D-PHY mode up to 4.5 Gbps per lane, available in FinFET processes for camera and display applications.

Industry’s First USB4 Silicon Success

USB4 offers up to 40Gbps speeds for incredibly fast connections. Join Synopsys to see the first demonstration of USB4 IP in silicon, along with real TX eyes for DesignWare USB4, DisplayPort, and USB 3.x IP.

Product Update: Highly Optimized DesignWare 112G/56G Ethernet PHY IP

Get the latest update on Synopsys’ PAM-4 DesignWare 112G/56G Ethernet PHY IP with optimized power, performance, and area, enabling true long reach connectivity.

Product Update: Advances in DesignWare Die-to-Die PHY IP

Hear the latest about Synopsys' DesignWare Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP addresses the power, bandwidth, and latency requirements of SoCs targeting hyperscale data center, AI, and networking applications. 

LE Audio Over Bluetooth with DesignWare IP

The video shows the new LE Audio using Synopsys’ DesignWare Bluetooth 5.2 PHY IP and Link Layer IP with isochronous channels, and ARC Data Fusion IP Subsystem with ARC EM9D Processor, running the LC3 codec supporting LE Audio. 

Hardware Security Verification Using Tortuga Logic Radix-S Software at ARC Summit 2019

Understand hardware security verification using the Tortuga Radix Software, which allows you to identify system-level security vulnerabilities that can exist at both the hardware and software levels. 

Automotive Trends Driving New SoC Architectures

The use of IP is prevalent in today’s new AI-enabled automotive SoCs for safety-critical ADAS applications. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet your evolving SoC design requirements.

IP Driving Automotive SoCs

If you are designing SoCs for ADAS, where safety and reliability are non-negotiable and a split second matters, then you want to know about Synopsys DesignWare IP for Automotive.

Maximizing SoC Throughput with Synopsys DesignWare CCIX IP

This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX  PHY and controller IP.

Test & Repair Requirements for Autonomous Vehicles

Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.

IP for Machine Learning Applications

The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements. 

55-nm IoT Platform

This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.

Under The Hood: What It Takes To Meet Automotive Compliance

This presentation provides insights into the technical specifications and design decisions for developing automotive grade IP, which helps accelerate compliance of automotive systems and ensures products meet automotive standards such as ISO 26262 functional safety, AEC-Q100 reliability testing and TS 16949 quality management.

 

Designing 7-nm IP, Bring It On Moore!

In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA req's. See how quantum effects impact FinFET designs in terms of fin width & height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance & power improvements.

What is ASIP Designer?

See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements. 

Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio

John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.

 

SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching

See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth.