DesignWare IP Videos

Hardware Security Verification Using Tortuga Logic Radix-S Software at ARC Summit 2019

Understand hardware security verification using the Tortuga Radix Software, which allows you to identify system-level security vulnerabilities that can exist at both the hardware and software levels. 

Automotive Trends Driving New SoC Architectures

The use of IP is prevalent in today’s new AI-enabled automotive SoCs for safety-critical ADAS applications. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet your evolving SoC design requirements.

What is USB4? USB, PCIe, and DisplayPort with a Single Type-C Connector

Jeff Ravencraft, President & COO of the USB-IF, and Synopsys discuss the new USB4 specification at USB Developer Days in September 2019.

DesignWare 112G Ethernet PHY IP in TSMC N7 Process

See the transmitter and receiver testing of Synopsys’ DesignWare 112G Ethernet PHY IP in TSMC’s N7 process. A 106.25Gb/s PAM-4 transmitter eye diagram shows good symmetry and height/width.  The receiver is tested with channels of up to 40dB of loss.  Performance metrics such as bit error rate (BER) and on-chip eye opening (via non-destructive 2D eye monitor) are reported. 

New ARC EV7x Vision Processor IP

The new EV7x Processor IP family with DNN accelerator offers performance up to 35 TOPS. The DNN can scale to 14,080 MACs with improved utilization, performance, bandwidth & power over EV6x. The EV7x’s vision engine improves SLAM & DSP performance, offers optional AES encryption for security & protection of coefficients & image data, & improved LSTM & RNN capabilities

IP Driving Automotive SoCs

If you are designing SoCs for ADAS, where safety and reliability are non-negotiable and a split second matters, then you want to know about Synopsys DesignWare IP for Automotive.

PCIe 5.0 Interoperability Success with DesignWare IP and Intel Test Chip

This video features Synopsys’ DesignWare IP for PCIe 5.0 interoperating with Intel’s 10-nm test chip running at 32GT/s data rates while operating at the L0 power state. Synopsys’ IP for PCIe is designed to support key features of the PCIe 5.0 specification, offering a low-risk solution for your AI, cloud computing, and other data-intensive SoCs. 

Enabling Concurrent Wireless Connectivity with DesignWare IP

This video showcases concurrent wireless connectivity across Bluetooth low energy, Thread, and Zigbee protocols using DesignWare IP. The Synopsys IP provides a low-power wireless interface solution for battery-operated, smart IoT devices with silicon-proven PHYs and controllers compliant with the latest versions of the standards. 

Maximizing SoC Throughput with Synopsys DesignWare CCIX IP

This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX  PHY and controller IP.

Developing RADAR for ADAS Applications using DesignWare® ARC® Processors

Learn about Synopsys’ Processor Solutions that meet high-computation and specialized processing requirements, enabling design teams to create highly-efficient and differentiated SoCs for RADAR applications.

 

Truphone eSIM and DesignWare tRoot Fx Hardware Secure Module

See how designers can provision any IoT device using Truphone’s iSIM solution and DesignWare tRoot Fx HSMs. Using Truphone bootstrap connectivity, the demo shows how in-the-field remote device activation is possible for any mobile operator and can remove the logistics and costs associated with physical SIM cards. 

Test & Repair Requirements for Autonomous Vehicles

Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.

Amazing AI SoCs

Amazing AI starts with silicon and software, designs that innovative teams around the world create every day. But in the end, it’s not just about chips. It’s about making transportation safer, making human connections stronger, and making our daily interactions more meaningful. 

IP for Machine Learning Applications

The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements. 

Sensor Connectivity with MIPI I3C

This video highlights the advantages of MIPI I3C for system-level sensor connectivity in mobile, automotive and IoT applications. A simple two-wire interface, I3C supports speeds up to 33 megabits per second and shares a 2-wire bus with multiple sensors. Synopsys DesignWare MIPI I3C IP supports the latest I3C specification and offers a complete solution for sensor connectivity. 

55-nm IoT Platform

This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.

Under The Hood: What It Takes To Meet Automotive Compliance

This presentation provides insights into the technical specifications and design decisions for developing automotive grade IP, which helps accelerate compliance of automotive systems and ensures products meet automotive standards such as ISO 26262 functional safety, AEC-Q100 reliability testing and TS 16949 quality management.

 

Selecting the right DDR Memory IP for Greatest Impact

SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. 

Secure Your IoT Device with Ultra-Low Power ARC Processors

Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum.

Designing 7-nm IP, Bring It On Moore!

In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA req's. See how quantum effects impact FinFET designs in terms of fin width & height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance & power improvements.

What is ASIP Designer?

See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements. 

Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio

John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.

 

SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching

See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth. 

Testing video of BrightCove Functionality

See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth.