DesignWare IP Videos

DesignWare MIPI C-PHY/D-PHY IP Performance at 24 Gbps

This video features the DesignWare MIPI C-PHY/D-PHY IP interoperating with an image sensor in C-PHY mode up to 3.5 Gsps per trio and D-PHY mode up to 4.5 Gbps per lane, available in FinFET processes for camera and display applications.

AI SoC Chats: Host Processor Interconnect IP for AI Accelerators

To support host-to-AI accelerator connectivity, AI chipsets can use PCI Express, CCIX, and/or CXL, and each have their benefits. Learn how to find the right interconnect for your AI SoC design.

AI SoC Chats: Primitive Math IP for AI

Learn about market trends and challenges around primitive math functions (floating point and integer math) in AI chipset development, and how DesignWare IP can help.

AI SoC Chats: Memory Interface IP - DDR, LPDDR, HBM, GDDR

When building AI SoCs, how do you choose the optimal memory interface? Learn about the market trends and challenges for DDR, LPDDR, HBM, and GDDR, and how Synopsys DesignWare IP can help.

AI SoC Trends: IP for In-Memory / Near-Memory Compute

Data-hungry AI chipsets have high compute intensity, leading to potential power consumption issues. Learn how memory selection, 3D stacking, and other innovations can address the challenges of making chips think like the human brain.

Product Update: New USB4 IP Solution

Are you ready for USB4? Join Gervais Fong and Eric Huang to learn more about this new 40Gbps standard and Synopsys DesignWare IP that helps bring your USB4-enabled design to market faster.

Product Update: High-Performance DesignWare Memory Interface IP

Get the latest update on Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E and how you can enable your DRAMs with the highest-performance, lowest-power, and lowest-area IP solution. 

Product Update: Protect IoT SoCs with DesignWare OTP NVM IP

JJoin Krishna Balachandran in this discussion on securing SoC data and IoT connections using Synopsys DesignWare OTP NVM IP. With more than 12 years of development and deployment by 500+ customers, Synopsys is the leader in antifuse-based OTP NVM IP. 

Product Update: Highly Optimized DesignWare 112G/56G Ethernet PHY IP

Get the latest update on Synopsys’ PAM-4 DesignWare 112G/56G Ethernet PHY IP with optimized power, performance, and area, enabling true long reach connectivity.

Product Update: Advances in DesignWare Die-to-Die PHY IP

Hear the latest about Synopsys' DesignWare Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP addresses the power, bandwidth, and latency requirements of SoCs targeting hyperscale data center, AI, and networking applications. 

Product Update: What's Hot in DesignWare IP for PCIe 5.0

Get the latest update on Synopsys' DesignWare Controller and PHY IP for PCIe 5.0 and how the low-latency, compact, power-efficient, and silicon-proven solution can enable your SoCs while reducing risk.

Product Update: Integrated DesignWare MIPI C-PHY/D-PHY IP

Get the latest update on Synopsys' DesignWare MIPI C-PHY/D-PHY IP solution and how the 24 Gbps total bandwidth can enable your camera, display, automotive, drone, and image sensor SoCs implemented in advanced FinFET processes. 

LE Audio Over Bluetooth with DesignWare IP

The video shows the new LE Audio using Synopsys’ DesignWare Bluetooth 5.2 PHY IP and Link Layer IP with isochronous channels, and ARC Data Fusion IP Subsystem with ARC EM9D Processor, running the LC3 codec supporting LE Audio. 

ULSee Real-Time Facial Recognition & Liveness Detection System using ARC EV62 Processors ARC Summit 2019

ULSee demonstrates their UL100 AI module, which integrates DesignWare ARC EV62 Processor IP, performing real-time facial recognition with very low power consumption. 

Hardware Security Verification Using Tortuga Logic Radix-S Software at ARC Summit 2019

Understand hardware security verification using the Tortuga Radix Software, which allows you to identify system-level security vulnerabilities that can exist at both the hardware and software levels. 

Automotive Trends Driving New SoC Architectures

The use of IP is prevalent in today’s new AI-enabled automotive SoCs for safety-critical ADAS applications. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet your evolving SoC design requirements.

IP Driving Automotive SoCs

If you are designing SoCs for ADAS, where safety and reliability are non-negotiable and a split second matters, then you want to know about Synopsys DesignWare IP for Automotive.

Maximizing SoC Throughput with Synopsys DesignWare CCIX IP

This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX  PHY and controller IP.

Developing RADAR for ADAS Applications using DesignWare® ARC® Processors

Learn about Synopsys’ Processor Solutions that meet high-computation and specialized processing requirements, enabling design teams to create highly-efficient and differentiated SoCs for RADAR applications.

 

Truphone eSIM and DesignWare tRoot Fx Hardware Secure Module

See how designers can provision any IoT device using Truphone’s iSIM solution and DesignWare tRoot Fx HSMs. Using Truphone bootstrap connectivity, the demo shows how in-the-field remote device activation is possible for any mobile operator and can remove the logistics and costs associated with physical SIM cards. 

Test & Repair Requirements for Autonomous Vehicles

Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.

Amazing AI SoCs

Amazing AI starts with silicon and software, designs that innovative teams around the world create every day. But in the end, it’s not just about chips. It’s about making transportation safer, making human connections stronger, and making our daily interactions more meaningful. 

IP for Machine Learning Applications

The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements. 

55-nm IoT Platform

This demo features an ASIC platform that increases performance, lowers power & reduces system cost for IoT apps. It shows apps such as voice, facial and gesture recognitions, and 9D sensor fusion. A collaboration between Synopsys, Brite and SMIC, the platform leverages Synopsys’ ARC Data Fusion IP Subsystem & Brite’s test chip in SMIC’s 55ULP.

Under The Hood: What It Takes To Meet Automotive Compliance

This presentation provides insights into the technical specifications and design decisions for developing automotive grade IP, which helps accelerate compliance of automotive systems and ensures products meet automotive standards such as ISO 26262 functional safety, AEC-Q100 reliability testing and TS 16949 quality management.

 

Secure Your IoT Device with Ultra-Low Power ARC Processors

Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum.

Designing 7-nm IP, Bring It On Moore!

In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA req's. See how quantum effects impact FinFET designs in terms of fin width & height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance & power improvements.

What is ASIP Designer?

See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements. 

Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio

John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.

 

SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching

See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth.