EDA
System
IP
SolvNetPlus
Training & Education
Extended product information and access for existing Synopsys customers below.
Please visit the Synopsys IP SHS page for more information.
Highlights & Key Features
- Hierarchical test accelerates SoC testing
- Automated test integration and validation of all IP/cores on SoC increases design and DFT productivity
- Flexible IP/core test scheduling optimizes test time and power
- Automated porting of IP/core patterns to SoC-level enables reuse of test patterns
- Optimized hierarchical IEEE 1500 network reduces area and signal routes
- Efficient on-chip e-fuse programming for IP calibration/trimming
- Certified to support the ISO 26262 ASIL D standard for automotive functional safety
Product Details
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