Cloud native EDA tools & pre-optimized hardware platforms
Fusion Compiler features a unique RTL-to-GDSII architecture that enables customers to reimagine what is possible from their designs and take the fast path to achieving maximum differentiation. It delivers superior levels of power, performance and area out-of-the-box, along with industry-best turnaround time. Fusion Compiler paired with Synopsys DSO.ai is driving even higher productivity while swiftly delivering results that you could previously only imagine.
Dr. Henry Sheng, group director of R&D, discusses how Synopsys Fusion Design Platform delivers a full-flow voltage optimization & closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.
When is 1+1 greater than 2? When using DesignWare Foundation IP & Fusion Compiler! Join Raymond and Yung in their discussion of a customer that benefited from the combination of Fusion Compiler’s machine learning and Foundation IP cells and macros.
Dr. Tobias Bjerregaard, Director of R&D at Synopsys, discusses how the latest innovations in power-grid integrity, deployed in Fusion Compiler in the form of dynamic-power-shaping (DPS) technology, is efficiently delivering more robust and reliable designs.
Sassine Ghazi, Synopsys' President and Chief Operating Officer, discusses how a revolution in digital design was started by creating a single data model for all design, and he describes how Fusion Compiler, the industry’s only RTL-to-GDSII design product, was formed.
To provide customers with better PPA and throughput for their design flows, Synopsys has re-invented design implementation with Fusion Compiler™.
Fusion Compiler is the result of the company’s bold initiative to build a new architecture from the ground up around a single, unified data-model that fuses synthesis, place and route (P&R) and signoff technologies in an unprecedented way to maximize PPA.