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Fusion Compiler
An innovative RTL-to-GDSII product that enables a new era in digital design implementation, Fusion Compiler offers new levels of predictable quality-of-results to address the challenges presented by the industry’s most advanced designs. It's unified architecture shares technologies across the RTL-to-GDSII flow to enable a highly convergent system delivering 20% better QoR and 2X faster time-to-results.
"Because of our successful evaluation results, we accelerated the deployment of Fusion Compiler..."
Seiichi Mori, Senior Vice President, Toshiba
Next Evolution of Digital Toolset
RTL-to-GDSII Synthesis Plus Place and Route Solution
White Paper
White Paper
Single Design Cockpit on the Fusion Data Model
Unified Physical Synthesis
RTL-to-GDSII System Signoff-quality Engines
NEW Fusion Compiler Enables Renesas to Accelerate Delivery of Next Gen Auto Designs
NEW Latest Release of Design Compiler NXT is Ready for Broad Availability
Fusion Design Platform Enables Successful Tapeout of Samsung Foundry's GAA Transistor SoC
Fusion Compiler Unveiled, Enabling 20 Percent Higher QoR and 2X Faster Time-to-Results
Benefits
- Comprehensive RTL-to-GDSII design system delivers up to 20% better performance, power, and area and 2X faster time-to-results
- Fusion data model architecture for unmatched capacity, scalability, and productivity
- Unified physical synthesis optimizations for best quality of results
- Common placement and 2D legalization engines for fast DRC convergence and design closure
- Accurate congestion estimation and prediction using route-driven estimate for overall convergence
- Complete flow power optimization including unique power-driven re-synthesis and knee-based optimization
- Physically-aware synthesis and advanced CTS to drive highest frequencies
- Leading foundry process certified FinFET and multi-patterning aware design
- Signoff timing, parasitic extraction, and power analysis eliminate design iterations
- Advanced area recovery algorithm from synthesis to post-route for best utilization
- Pervasive parallelization with multi-threaded and distributed processing technologies for maximum throughput