Cloud native EDA tools & pre-optimized hardware platforms
Fusion Compiler delivers superior levels of power, performance and area out-of-the-box, along with industry-best turnaround time. Hear our R&D experts discus the latest innovations and how Fusion Compiler can help you achieve simply better PPA.
Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL-to-GDSII data model, delivers a full-flow voltage optimization and closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.
When is 1+1 greater than 2? When using DesignWare Foundation IP & Fusion Compiler! Join Raymond and Yung in their discussion of a customer that benefited from the combination of Fusion Compiler’s machine learning and Foundation IP cells and macros.
Dr. Tobias Bjerregaard, Director of R&D at Synopsys, discusses how the latest innovations in power-grid integrity, deployed in Fusion Compiler in the form of dynamic-power-shaping (DPS) technology, is efficiently delivering more robust and reliable designs.
Dr. Aiqun Cao, VP of Engineering at Synopsys, discusses how Fusion Compiler’s unified physical synthesis and common optimization framework enables full-flow concurrent clock and data (CCD) optimization, while ensuring physical convergence downstream.
Dr. Henry Sheng, group director of R&D at Synopsys, discusses how Fusion Compiler delivers signoff-accurate PPA on high-performance, low-power designs at advanced nodes, and accelerates design schedules by eliminating late surprises and iterations.