RedHawk Analysis Fusion in IC Compiler II

In-Design Power Integrity Analysis and Fixing

The IC Compiler™ II with RedHawk™ Analysis Fusion integration introduces in-design power integrity analysis and fixing capabilities in designers' flows offering signoff accuracy results during the physical design step.  Designed to help block-level and top-level engineers converge on their challenging power integrity requirements, the industry’s most used RedHawk signoff engines are leveraged to enable physical designers to analyze and modify their design all within the same environment.

Tower of Power

Listen to Amelia Dalton of EEJournal and Kenneth Chang discuss
RedHawk Analysis Fusion and near threshold voltage computing


“RedHawk Analysis Fusion complements ANSYS’ industry-standard power integrity and reliability analyses, and enables designers to unlock better PPA” 

-John Lee, vice president and general manager at ANSYS


  • IC Compiler II with RedHawk Analysis Fusion is an integrated environment created for physical designers to do in-design rail analysis and repair
  • Includes common analysis features such as connectivity checks and static and dynamic analysis coverage, with and without vector
  • Leverage automatic in-design rail fixing capabilities including PG augmentation and missing via insertion
  • Easy-to-learn.  Easy-to-use.  Built for the physical design engineer, RedHawk engines are called under the hood, transparent to the user
  • Reduce the pains related to manually translating results from rail analysis and applying fixes in physical design through RedHawk Analysis Fusion automatic setup
  • Run early-and-often to reduce overall schedule time and iterations
  • Quickly visualize IR drop maps in IC Compiler II cockpit and allow users to do immediate what-if analysis for accelerated debugging
  • Delivers a complete power flow, compliments your signoff power integrity tool