- All Products
- Software Integrity
- Semiconductor IP
- Verification
- Design
- Silicon Engineering
- Application Security Services
- Dynamic Analysis (DAST)
- Mobile Application Security
- Penetration Testing
- Managed Static Analysis
- All Services
- Software Security
- Silicon Design
- Community
- About Us
< All Products
< All Products
< All Products
< All Products
< All Products
< All Products
< overview
All Products
+ Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering + Optical Solutions< Software Integrity
< Software Integrity
Application Security Services
Dynamic Analysis (DAST) Mobile Application Security Penetration Testing Managed Static Analysis< Software Integrity
< Software Integrity
< Software Integrity
Blog
< Software Integrity
Support
< overview
Software Integrity
+ Application Security Products + Application Security Services + Resources + Training & Education Blog Support< Semiconductor IP
< Semiconductor IP
Memories & Libraries
Logic Libraries Memory Compliers Duet Packages HPC Design Kit Embedded Test & Repair Non-Volatile Memory< Semiconductor IP
< Semiconductor IP
Processor Solutions
ARC Processors Embedded Vision Processors Development Tools Operating Systems Ecosystems ASIP Tools< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< overview
< Verification
< Verification
< Verification
< Design
< Design
< Design
< overview
< Silicon Engineering
< overview
< main menu
< Solutions
< Solutions
Industry Solutions
Automotive Cloud Computing Financial Services Industrial Controls Systems Healthcare Mobile Devices< Solutions
< overview
< All Services
< All Services
< All Services
< overview
< Software Security
Software Security Professional Services
Embedded Software Testing Insider Threat Detection Red Teaming Secure Coding Guidelines Software Architecture & Design Thick Client Testing< Software Security
Managed Services
< Software Security
Program Development & Design
Maturity Model (BSIMM) Maturity Action Plan (MAP) Policies & Standards Security Metrics Software Security-in-a-Box< Software Security
< Software Security
Support
< overview
< Silicon Design
< Silicon Design
< Silicon Design
< Silicon Design
< main menu
< Community
Community
Community Overview< Community
< Community
< Community
Interoperability
ARC Access HAPS Connect HSPICE Integrator In-Sync System-Level Catalyst TAP-in VC Apps Access< Community
< Community
< Community
< overview
Community
+ Community + SNUG + Partners + Interoperability + Academic Programs + Company Blogs + BSIMM< About Us
< About Us
< About Us
< About Us
< About Us
Standard Cell Libraries
Synopsys' DesignWare® Logic Libraries provide a broad portfolio of high-speed, high-density and low-power standard cell libraries, providing a complete standard cell platform solution for a wide variety of system-on-chip (SoC) designs. In addition to Synopsys' silicon-proven standard cell libraries, available Power Optimization Kits (POKs) and Engineering Change Order (ECO) Kits deliver outstanding performance, with low power and small area in the advanced nodes of leading foundries.
Ideal for tablet, smartphone, cell phone, graphics, networking, storage and other high-performance applications requiring low power and high density, Synopsys' DesignWare Logic Libraries and Memory Compilers provide a unique set of options that enable SoC designers to optimize their products for speed, area, dynamic power, standby power and cost.
Multiple Architectures, Multiple VTs, Multi-Channel LengthsThe standard cell libraries provide three separate architectures, high-speed (HS), high-density (HD) and ultra high-density (UHD), to optimize circuits for performance, power and area tradeoffs.
The standard cell libraries include multiple voltage threshold implants (VTs) at most processes from 180-nm to 65-nm and support multiple channel (MC) gate lengths to minimize leakage power at 40-nm and below.
DesignWare Embedded Memories and Logic Libraries are available for multiple foundries and process technologies, including GLOBALFOUNDRIES, SMIC, TSMC, and UMC.
DesignWare Duet Embedded Memories and Logic Libraries Datasheets
GLOBALFOUNDRIES 40LP-Duet Embedded Memories and Logic Libraries Datasheet GLOBALFOUNDRIES 55LPe-Duet Embedded Memories and Logic Libraries Datasheet SMIC 40LL-Duet Embedded Memories and Logic Libraries Datasheet SMIC 65LL-Duet Embedded Memories and Logic Libraries Datasheet TSMC 16FF+ -Duet Embedded Memories and Logic Libraries Datasheet TSMC 16FFC-Duet Embedded Memories and Logic Libraries Datasheet TSMC 28HP-Duet Embedded Memories and Logic Libraries Datasheet TSMC 28HPC+ -Duet Embedded Memories and Logic Libraries Datasheet TSMC 28HPC-Duet Embedded Memories and Logic Libraries Datasheet TSMC 28HPM-Duet Embedded Memories and Logic Libraries Datasheet TSMC 40LP-Duet Embedded Memories and Logic Libraries Datasheet TSMC 65LP-Duet Embedded Memories and Logic Libraries Datasheet UMC 28HLP-Duet Embedded Memories and Logic Libraries Datasheet UMC 28HPC-Duet Embedded Memories and Logic Libraries Datasheet UMC 40LP-Duet Embedded Memories and Logic Libraries Datasheet UMC 40ULP - Duet Embedded Memories and Logic Libraries Datasheet
Highlights
Features
- Maximum Performance
- High-performance libraries for critical paths of GHz processors
- Close timing in fewer iterations without sacrificing area or power
- Minimum Power
- Multi-channel libraries for 4X-5X static power reduction
- Power Optimization Kits with over 200 cells
- Support for low-power UPF and CPF EDA flows
- Maximum Density
- Patented NXT standard cell architectures for highest routing utilization
- Multiple cell heights (# tracks) per process for optimal tradeoffs
- Hand-crafted layout for maximum density
- Deep cell set of functions and drive strengths for optimal cell choice
- Optimal pin placement for highest routed density
- High Yield
- Design-for-manufacturing (DFM)-aware design and validation
- Redundant contacts
- Electro-migration (EM)-compliant at highest speeds
- Comprehensive Solution
- Electrically, physically and EDA-view aligned with DesignWare Embedded Memory products
- Multi-VDD characterization with low voltage and overdrive PVTs
- Multiple Libraries per Process Node
- Base Libraries include cell set in multiple architectures/ VTs at minimum channel length
- Multiple Channel Length Libraries (MC) for leakage reduction at 40-nm and smaller and to reduce die-to-die leakage and timing variability
- Power Optimization Kits enable shut-down and multiple voltage domains
- ECO Kits enable metal-only post-silicon fixes to cost-effectively address bugs
- High Performance Core (HPC) Design Kits offered at 40-nm and smaller with datapath cells and multi-bit flip-flops
- Metal-programmable libraries for flexible, metal-only design changes over life of product
- Ultra Low Leakage Libraries provide up to 100X leakage reduction for building always-on blocks
- Multiple Cell Architectures for Optimal Power, Performance and Area
- High-Speed (tall) library for the ultimate in performance for critical paths
- High-Density (short) library for general purpose logic with balanced PPA
- Ultra-High Density (shortest) library for lowest power, lowest cost and highest density
- Optimized Cell Sets
- Rich synthesis-friendly cell set with multiple cell variants and drive strengths
- Specialty cells such as integrated clock gaters (ICG), multi-bit flip-flops and routing support cells
- Accurate Characterization
- HSPICE® accuracy
- Propagation delays and constraints (Setup, Hold, Removal & Recovery, Minimum Pulse Width)
- Corner specific extraction at advanced nodes
- EDA Views
- Liberty® Timing, Noise and Power, CCS Timing, Noise and ECSM Timing
- Other specialty models
- Availability of Process, Voltage and Temperature (PVT) Characterization Corners
- Standard, overdrive and low voltage PVT clusters for timing and leakage
- PVTs aligned with DesignWare Memory Compiler PVTs
- Custom PVT development available
- Silicon proven using Split Lots at Advanced Nodes
- Correlated to EDA models
- Low voltage testing to VDDMin