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Synopsys' DesignWare® Logic Libraries provide a broad portfolio of high-speed, high-density and low-power standard cell libraries, providing a complete standard cell platform solution for a wide variety of system-on-chip (SoC) designs. In addition to Synopsys' silicon-proven standard cell libraries, available Power Optimization Kits (POKs) and Engineering Change Order (ECO) Kits deliver outstanding performance, with low power and small area in the advanced nodes of leading foundries.
Ideal for tablet, smartphone, cell phone, graphics, networking, storage and other high-performance applications requiring low power and high density, Synopsys' DesignWare Logic Libraries and Memory Compilers provide a unique set of options that enable SoC designers to optimize their products for speed, area, dynamic power, standby power and cost.
Multiple Architectures, Multiple VTs, Multi-Channel Lengths
The standard cell libraries provide three separate architectures, high-speed (HS), high-density (HD) and ultra high-density (UHD), to optimize circuits for performance, power and area tradeoffs.
The standard cell libraries include multiple voltage threshold implants (VTs) at most processes from 180-nm to 65-nm and support multiple channel (MC) gate lengths to minimize leakage power at 40-nm and below.
DesignWare Duet Embedded Memories and Logic Libraries Datasheets
 28HP-TSMC Datasheet
28HPM-TSMC Datasheet
40G-TSMC Datasheet
40LL-SMIC Datasheet
40LP-GLOBALFOUNDRIES Datasheet
40LP-TSMC Datasheet
40LP-UMC Datasheet
65LL-SMIC Datasheet
65LP-TSMC Datasheet
- Maximum Performance
- High-performance libraries for critical paths of GHz processors
- Close timing in fewer iterations without sacrificing area or power
- Minimum Power
- Multi-channel libraries for 4X-5X static power reduction
- Power Optimization Kits with over 200 cells
- Support for low-power UPF and CPF EDA flows
- Maximum Density
- Patented NXT standard cell architectures for highest routing utilization
- Multiple cell heights per process (~7, ~9 and ~12 track) for optimal tradeoffs
- Hand-crafted layout for maximum density
- Deep cell set of functions and drive strengths for optimal cell choice
- High Yield
- Design-for-manufacturing (DFM)-aware design and validation
- Redundant contacts
- Electro-migration (EM)-compliant at highest speeds
- Comprehensive Solution
- Electrically, physically and EDA-view aligned with DesignWare Embedded Memory products
- Multi-VDD characterization with low voltage and overdrive PVTs
- Multiple Libraries per Process Node
- Base Libraries include cell set in multiple architectures/ VTs at minimum channel length
- Multiple Channel Length Libraries (MC) for leakage reduction at 40-nm and smaller and to reduce die-to-die leakage and timing variability
- Power Optimization Kits enable shut-down and multiple voltage domains
- ECO Kits enable metal-only post-silicon fixes to cost-effectively address bugs
- High Performance Kits (HPK) offered at 28-nm and smaller with high-speed datapath cells
- Metal-programmable libraries for flexible, metal-only design changes over life of product
- Multiple Cell Architectures for Optimal Power, Performance and Area
- High-Speed ~12 track library for the ultimate in performance for critical paths
- High-Density ~9 track library for general purpose logic with balanced PPA
- Ultra-High Density ~7 track library for lowest power, lowest cost and highest density
- Optimized Cell Sets
- Rich synthesis-friendly cell set with multiple cell variants and drive strengths
- Specialty cells such as integrated clock gaters (ICG) and routing support cells
- Accurate Characterization
- HSPICE® accuracy
- Propagation delays and constraints (Setup, Hold, Removal & Recovery, Minimum Pulse Width)
- Corner specific extraction at advanced nodes
- EDA Views
- Liberty® Timing, Noise and Power, CCS Timing, Noise and ECSM Timing
- Other specialty models
- Availability of Process, Voltage and Temperature (PVT) Characterization Corners
- Standard, overdrive and low voltage PVT clusters for timing and leakage
- PVTs aligned with DesignWare Memory Compiler PVTs
- Custom PVT development available
- Silicon proven using Split Lots at Advanced Nodes
- Correlated to EDA models
- Low voltage testing to VDDMin
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