TSMC N6 Foundation IP Datasheet
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality foundation IP including high-speed (HS), high-density (HD), and
ultra high-density (UHD) memory compilers, logic libraries and IO solutions
that are extensively proven in silicon with billions of units shipping in volume production, reducing project risk, and speeding time-to-market.
Optimized for TSMC’s 6nm FinFET process technology, the DesignWare® Duet
Packages of Embedded Memories and Logic Libraries include standard cells,
SRAMs, register files, ROMs, HPC Design Kits, Power Optimization Kits (POKs) and optional overdrive / low voltage PVTs, UHD memory, and TCAM memory compilers, multi-channel cells, GPIO, Specialty IO, and memory built-in self-test (BIST) and repair.
This IP solution enables designers of mobile, and
high performance compute applications that require high speed, low leakage, and low power to achieve the best combination of performance, power, and area (PPA) for their SoC designs.
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