There is no margin for error in leading-edge chip design and selecting the right tools for design signoff is critical to silicon success. Synopsys offers a broad and integrated portfolio of state-of-the art design analysis and signoff products, all based on the golden signoff foundation customers have come to trust. Synopsys continues to lead the industry in design signoff innovations to address the growing challenges of design complexity, scale and new requirements for chip design on advanced process nodes. 

Accelerate Design Closure

Synopsys' design analysis and signoff solution includes a broad portfolio of products for static timing analysis, advanced signal integrity, power and  power integrity, parasitic extraction, ECO closure, transistor-level analysis and library characterization. The native integration of signoff technologies with  IC Compiler™ II  and  Fusion Compiler allows physical designers to confidently realize the full performance-power-area (PPA) potential of the design with the fastest path to design closure.

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Solution Overview

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Timing and ECO Closure

Synopsys’ PrimeTime® solution delivers fast, memory-efficient scalar and multicore static timing analysis, distributed multi-scenario analysis and ECO fixing using POCV and variation-aware modeling.

Synopsys PrimeClosure is the industry’s first AI-driven golden signoff ECO closure solution and is  integrated with industry-golden Synopsys PrimeTime Static Timing Analysis and Synopsys Fusion Compiler™ RTL-to-GDSII implementation solution to accelerate electronic-design power-performance-area closure time-to-results (TTR).

Synopsys PrimeShield solution provides the industry’s fastest design robustness analysis solution built on golden PrimeTimeSTA and accelerated with breakthrough machine learning technology. 

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Transistor-level Signoff

Synopsys NanoTime is the golden timing signoff solution for transistor-level design for CPU datapaths, embedded memories and complex AMS IP blocks. 

Its seamless integration with Synopsys’ PrimeTime® product enables full-chip analysis of designs that includes both gate- and transistor-level blocks. Synopsys NanoTime is a key component of the Synopsys custom design verification solution that includes Synopsys CustomSim® and HSPICE for circuit simulation and Synopsys ESP for symbolic simulation-based equivalence checking.

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Power and Power-Integrity Closure

Synopsys PrimePower analyzes power dissipation for block and full-chip designs starting from RTL, through implementation, and leading to power signoff.

RedHawk Analysis Fusion provides early, comprehensive in-design power integrity analysis and fixing in Synopsys IC Compiler™II and Synopsys Fusion Compiler™ solutions, enabling signoff accuracy during physical design implementation. 

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Library Characterization

The Synopsys SiliconSmart® solution provides fast, accurate, and advanced node proven library characterization for standard cells, I/O and memory.  Synopsys PrimeLib is the next-generation, unified library characterization and validation solution, providing ultra-fast, signoff-quality libraries and is optimized for scaling and performance for cloud and cluster computing workloads.

Synopsys SiliconSmart and Synopsys PrimeLib innovative technologies utilize embedded gold-reference SPICE engines to provide a characterization speed-up of advanced Liberty models used by Synopsys PrimeTime static timing analysis to accurately account for effects seen in ultra-low-voltage FinFET processes that impact timing.

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Parasitic Modeling and Extraction

The Synopsys StarRC™ solution provides golden signoff parasitic extraction for silicon accurate results supporting advanced foundry nodes and design flows.​

The Synopsys QuickCap® NX solution is the golden extraction reference tool for advanced node process modeling and high accuracy library characterization.