Synopsys Timing Constraints Manager, built on FishTail Design Automation technology, offers a unique low-noise approach for designers to improve chip design by verifying, generating, and managing SDC constraints. Synopsys Timing Constraints Manager is a complete solution for the management of design constraints as chip-implementation progresses. Designers can drive chip-implementation using comprehensive and accurate constraints earlier in the design cycle leading to improved PPA, shorter overall TAT and elimination of the risk of silicon failure caused by incorrect timing exceptions. Designers can also use Synopsys Timing Constraints Manager for promotion and demotion of constraints. Synopsys Timing Constraints Manager technology provides the ability to take a large, complex RTL design or gate-level netlist and automatically abstract only the required behavior and structure with respect to the task being performed.
Superior SDC Verification QoR Using Formal Technology
Critical Bug Finding
Using Sophisticated Timing Exception Verification and SDC Management Solutions
Highly Automated and Easy-to-Use
Automated Constraints Promotion Methodology from IP to SoC for Complex Designs